- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373968 > AD9805 (Analog Devices, Inc.) Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors PDF資料下載
參數(shù)資料
| 型號： | AD9805 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| 中文描述： | 完成12-Bit/10-Bit 6 MSPS的防治荒漠化公約/ CIS信號處理器 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 240K |
| 代理商： | AD9805 |
AD9807/AD9805
–14–
REV. 0
3-Channel SHA Operation
T his mode of the AD9807/AD9805 enables 3-channel simulta-
neous sampling; it differs from the CDS sampling mode in that
the CDS functions are replaced with sample-and-hold amplifiers
(SHAs). CDSCL K 1 becomes the sample-and-hold clock;
CDSCLK 2 is tied to ground. T he input is sampled on the
falling edge of CDSCLK 1. T he input signals must be either dc
coupled and level shifted, or dc restored prior to driving the
VINR, VING, and VINB pins of the AD9807/AD9805 (clamp
mode must be disabled). T he input signal in this mode is
ground-referenced. T he offsets of the three input channels are
modified by the values stored in the input offset registers. T he
part does not invert the input signals prior to amplification by
the PGAs; the settings in the corresponding PGA Gain Registers
determine the gains of the PGAs. T hese outputs from the
PGAs are then routed through a high speed multiplexer to a
12-bit A/D converter (10-bit for AD9805) for digitization; the
multiplexer cycles between the red, green and then blue
channels. After digitization, the data is modified by the amount
indicated in the Odd and Even Offset Registers. A digital
subtracter allows additional pixel rate offset modification of
each color based on the values written to the OFFSET data bus.
Finally, a digital multiplier allows pixel rate gain modification
of each color based on the values written to the GAIN data bus.
Latency for the red, green and blue channels is 6 ADCCLK
cycles (9 cycles for the gain and offset bus; see Figure 13).
T he ST RT LN signal indicates the first red, green and blue
pixels in a scan line and the red channel is always the first pixel
digitized. T he state of ST RT LN is evaluated on the rising
edges of ADCCLK . When ST RT LN is low, the internal
circuitry is reset on the next rising edge of ADCCLK ; the
multiplexer is switched to the red channel and the odd/even
circuitry is configured to expect even pixels. After ST RT LN
goes high, the first set of pixels is assumed to be even. Consecu-
tive sets of pixels (red, green and blue) are assumed to alternate
between odd and even pixel sets.
1-Channel Operation with CDS
T his mode of the AD9807/AD9805 enables single-channel, or
monochrome, sampling. T he CCD waveform is ac coupled to
either the VINR, VING, and VINB pin of the AD9807/AD9805
where it is biased at an appropriate voltage level using the on-
chip clamp; the input may alternatively be dc coupled if it has
already been appropriately level shifted. Bits 6 and 7 in the
Configuration Register select the desired input. T he internal
CDS takes two samples of the incoming pixel data: the first
sample (CDSCLK 1) is taken during the reset time while the
second sample (CDSCL K 2) is taken during the video, or data,
portion of the input pixel. T he offset of the input signal is
voltage
difference
of the reset level and video level is inverted and
amplified by the PGA; the setting in the corresponding PGA
Gain Register determines the gain of the PGA. T he output
from the PGA is then routed through a high-speed multiplexer
to a 12-bit A/D converter (10-bit for AD9805) for digitization;
the multiplexer does not cycle in this mode. After digitization,
the data is modified by the amount indicated in the Odd and
Even Offset Registers. A digital subtracter allows additional
pixel rate offset modification of the signal based on the values
written to the OFFSET data bus. Finally, a digital multiplier
allows pixel rate gain modification of the signal based on the
values written to the GAIN data bus. Latency is 6 ADCCLK
cycles (7 cycles for the gain and offset bus; see Figure 14).
T he state of ST RT L N is evaluated on the rising edges of
ADCCLK . When ST RT LN is low, the internal circuitry is
reset on the next rising edge of ADCCLK ; the odd/even
circuitry is configured to expect an even pixel. After ST RT LN
goes high, the first pixel is assumed to be even. Consecutive
pixels (red, green or blue) are assumed to alternate between odd
and even. T he blue and green channels are recommended for
single channel operation to achieve the maximum sampling rate;
if using red, invert ADCCLK as shown in Figure 1d.
1-Channel SHA Operation
T his mode of the AD9807/AD9805 enables single-channel, or
monochrome sampling; it differs from the CDS monochrome
sampling mode in that the CDS function is replaced with a
sample-and-hold amplifier (SHA). CDSCLK 1 becomes the
sample-and-hold clock; CDSCLK 2 is tied to ground. T he
input is sampled on the falling edge of CDSCLK 1. T he input
waveform would typically be either dc coupled and level shifted,
or dc restored prior to driving either the VINR, VING and
VINB pins of the AD9807/AD9805 (clamp mode must be
disabled).
Bits 6 and 7 in the Configuration Register select the desired
input. T he input signal in this mode is ground referenced. T he
input signal is not inverted prior to amplification by the PGA;
the setting in the corresponding PGA Gain Register determines
the gain of the PGA. T he offset of the input signal is modified
by the value stored in the input offset register. T his signal is
then routed through a high speed multiplexer to a 12-bit A/D
converter (10-bit for AD9805) for digitization; the multiplexer
does not cycle in this mode. After digitization, the data is
modified by the amount indicated in the Odd and Even Offset
Registers. A digital subtracter allows additional pixel rate offset
modification of the signal based on the values written to the
OFFSET data bus. Finally, a digital multiplier allows pixel rate
gain modification of the signal based on the values written to the
GAIN data bus. Latency is 6 ADCCLK cycles (7 cycles for
gain and offset; see Figure 15).
T he state of ST RT L N is evaluated on the rising edges of
ADCCLK . When ST RT LN is low, the internal circuitry is
reset on the next rising edge of ADCCLK ; the odd/even
circuitry is configured to expect an even pixel. After ST RT LN
goes high, the first pixel is assumed to be even. Consecutive
pixels (red, green or blue) are assumed to alternate between odd
and even. T he blue and green channels are recommended for
single channel operation to achieve the maximum sampling rate;
if using red, invert ADCCLK as shown in Figure 1f.
2-Channel Bayer Mode Operation with CDS
T his mode of the AD9807/AD9805 enables Bayer Mode. T he
CCD waveform is ac coupled to both the VING and VINB pins
of the AD9807/AD9805 where it is biased at an appropriate
voltage level using the on-chip clamp; the input may alterna-
tively be dc coupled if it has already been appropriately level
shifted. T he internal CDS takes two samples of the incoming
pixel data: the first sample (CDSCLK 1) is taken during the
reset time while the second sample (CDSCLK 2) is taken during
the video, or data, portion of the input pixel. T he offset of the
input signal is modified by the value stored in the input offset
register. T he voltage difference of the reset level and video level
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9805JS | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9807 | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9807JS | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9806 | Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9806KST | Complete 10-Bit 18 MSPS CCD Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9805JS | 制造商:Analog Devices 功能描述:CCD/CIS Signal Processor 64-Pin PQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT ANALOG FRONT END DOC SCANNER - Bulk |
| AD9806 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9806KST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MSPS CCD SIGNAL PROCESSOR - Bulk |
| AD9806KSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V 48-Pin LQFP T/R |
| AD9806KSTZ | 功能描述:IC CCD SIGNAL PROC 10BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。