- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375249 > AD9803JST (ANALOG DEVICES INC) CCD Signal Processor For Electronic Cameras PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9803JST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor For Electronic Cameras |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 3/19頁(yè) |
| 文件大?。?/td> | 179K |
| 代理商： | AD9803JST |
第1頁(yè)第2頁(yè)當(dāng)前第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
–3–
REV. 0
AD9803
CCD-MODE SPECIFICATIONS
P
arameter
Min
Typ
Max
Units
POWER CONSUMPTION
V
DD
= 2.7
V
DD
= 2.8
V
DD
= 3.0
MAXIMUM CLOCK RATE
150
170
185
mW
mW
mW
18
MHz
CDS
Gain
Allowable CCD Reset Transient
1
Max Input Range Before Saturation
1
0
500
dB
mV
mV p-p
1000
PGA
Max Input Range
Max Output Range
Digital Gain Control (See Figure 26)
Gain Control Resolution
Minimum Gain (Code 0)
Low Gain (Code 207)
Medium Gain (Code 437)
High Gain (Code 688)
Max Gain (Code 1023)
Analog Gain Control (See Figure 25)
PGACONT1 = 0.7 V, PGACONT2 = 1.5 V
PGACONT1 = 1.8 V, PGACONT2 = 1.5 V
1000
1000
mV p-p
mV p-p
10 (Fixed)
–1.5
4
15
26
Bits
dB
dB
dB
dB
dB
–3.5
0
0
8
22
32
30
4.5
26
dB
dB
BLACK-LEVEL CLAMP
Clamp Level (Selected by the Serial I/F)
CLP(0) (E-Reg 00)
CLP(1) (E-Reg 01)
CLP(2) (E-Reg 10)
CLP(3) (E-Reg 11)
Even-Odd Offset
2
SIGNAL-TO-NOISE RATIO
3
(@ Minimum PGA Gain)
TIMING SPECIFICATIONS
4
Pipeline Delay
Even-Odd Offset Correction Disabled
Even-Odd Offset Correction Enabled
Internal Clock Delay
5
(t
ID
)
Inhibited Clock Period (t
INHIBIT
)
Output Delay (t
OD
)
Output Hold Time (t
HOLD
)
ADCCLK, SHP, SHD, Clock Period
ADCCLK Hi-Level, Or Low Level
SHP, SHD Minimum Pulsewidth
6
SHP Rising Edge to SHD Rising Edge
34
50
66
18
±
0.5
61
LSB
LSB
LSB
LSB
LSB
dB
5
7
3
Cycles
Cycles
ns
ns
ns
ns
ns
ns
ns
ns
15
20
2
47
20
10
20
55.6
28
14
28
NOTES
1
Input Signal Characteristics defined as shown:
OPTIC50mV MAX
RE500mV TYP
INRANGE
2V MAX
INPUT SIGNAL
2
Even-Odd Offset is described under the Theory of Operation section. The Even-Odd Offset is measured with the Even-Off Offset correction enabled.
3
SNR = 20 log
(Full-Scale Voltage/RMS Output Noise).
4
20 pF loading; timing shown in Figure 1.
5
Internal aperture delay for actual sampling edge.
6
Active Low Clock Pulse Mode (C-Reg 00).
Specifications subject to change without notice.
(T
MIN
to T
MAX
, ACVDD = ADVDD = DVDD = +2.8 V, f
SHP
= f
SHD
= f
ADCCLK
= 18 MHz unless otherwise
noted)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9804 | Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9804JST | Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9850BRS | CMOS, 125 MHz Complete DDS Synthesizer |
| AD9850 | CMOS,125 MHz Complete DDS Synthesizer |
| AD9851BRS | CMOS 180 MHz DDS/DAC Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9803JST-28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9803JSTRL-28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9804 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9804AJST | 制造商:Analog Devices 功能描述:CCD Signal Processor 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MHZ NO PXGA - Tape and Reel |
| ad9804ajstrl | 制造商:Analog Devices 功能描述:CCD Signal Processor 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MHZ NO PXGA - Tape and Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。