- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373968 > AD9802 (Analog Devices, Inc.) .50" x 50 Black/Clear 240 Industrial Label Supply RoHS Compliant: NA PDF資料下載
參數(shù)資料
| 型號： | AD9802 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | .50" x 50 Black/Clear 240 Industrial Label Supply RoHS Compliant: NA |
| 中文描述： | CCD信號處理器電子照相機 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 366K |
| 代理商： | AD9802 |
AD9802
–12–
REV. 0
T he disadvantage of this circuit is that the control voltage will
be supply dependent. If additional precision is required, an
external op amp can be used to amplify the VREFT (1.75 V) or
VREFB (1.25 V) pins on the AD9802 to the desired voltage
level. T hese reference voltages are stable over the operating
supply range of the AD9802. Low power, low cost, rail-to-rail
output amplifiers like the AD820, OP150 and OP196 are speci-
fied for 3 V operation. Alternatively, a precision voltage refer-
ence may be used. T he REF193 from Analog Devices features
low power, low dropout performance, maintaining a 3 V output
with a minimum 3.1 V supply when lightly loaded.
Power and Grounding Recommendations
T he AD9802 should be treated as an analog component when
used in a system. T he same power supply and ground plane
should be used for all of the pins. In a two-ground system, this
requires that the digital supply pins be decoupled to the analog
ground plane and the digital ground pins be connected to ana-
log ground for best noise performance. If any pins on the
AD9802 are connected to the system digital ground, then noise
can capacitively couple inside the AD9802 (through package
and die parasitics) from the digital circuitry to the analog
circuitry. Separate digital supplies can be used, particularly if
slightly different driver supplies are needed, but the digital
power pins should still be decoupled to the same point as the
digital ground pins (analog ground plane). If the AD9802 digi-
tal outputs need to drive a bus or substantial load, a buffer
should be used at the AD9802’s outputs, with the buffer refer-
enced to system digital ground. In some cases, when system
digital noise is not substantial, it is acceptable to split the
ground pins on the AD9802 to separate analog and digital
ground planes. If this is done, be sure to connect the ground
pins together at the AD9802.
T o further improve performance, isolating the driver supply
DRVDD from DVDD with a ferrite bead can help reduce kick-
back effects during major code transitions. Alternatively, the use
of damping resistors on the digital outputs will reduce the out-
put rise times, reducing the kickback effect.
E valuation Board
An evaluation board for the AD9802 is available. T he board
includes circuitry for manual PGA gain adjustment, input signal
buffering, and logic level translation for 3 V or 5 V digital signals.
Documentation for the AD9802-EB is included, consisting of a
board description, schematic and layout information.
AD9801/AD9802 E VALUAT ION BOARD DE SCRIPT ION
Power Supply Connectors
J1
VDD: +3 V supply for the AD9801/AD9802. Data
sheet specifications are given for +3.15 V. Operational
range is from +3 V to +3.5 V.
J2
AVCC: +5 V supply for the AD8047 buffer, and for the
PGACONT and PIN potentiometers. If the buffer am-
plifier is not needed, AVCC may be connected to the
VDD supply.
J3
AVSS: –5 V supply for the AD8047 buffer. If the buffer
amplifier is not needed, AVSS may be connected to J4.
J4
AGND : T his is the analog ground plane for the
AD9801/AD9802 and the buffer amplifier. T he two
ground planes are already connected together in one
place on the evaluation board.
J5
D GND : T his is the digital ground plane for the
LVX C3245 transceivers. T he two ground planes are
already connected together in one place on the evalua-
tion board.
J6
+3D: +3 V digital supply for the LVX C3245 transceivers.
J7
+3/5D: +3 V or +5 V digital supply for the LVX C3245
transceivers. T his voltage determines the logic compat-
ibility of the evaluation board. If 3 V clock levels and
3 V digital output levels are to be used, connect +3 V to
J7. If +5 V clock levels and +5 digital output levels are
to be used, connect +5 V to J7.
Input Connectors
J8
DIN: Unbuffered input to the AD9801/AD9802. T his
input is 50
terminated by R4, which may be removed
if no termination is required. See Input Configurations
for more information.
J9
VIN: Input to the AD8047 buffer amplifier. T his
input is 50
terminated by R5, which may be re-
moved if no termination is required. T his op amp
can be used as a buffer to drive the DIN pin on the
AD9801/AD9802, or as a buffer for driving the direct
ADC input on the AD9802. See Input Configurations
and the AD9802 data sheet for more information.
Clock Connectors
J10
CLPDM
J11
SHD
J12
SHP
J13
CLPOB
J14
PBLK
J15
ADCCLK
All of the clock inputs are 50
terminated and buffered by an
LVX C3245 transceiver. T he supply level at J7 determines the
input clock level compatibility. T he outputs of the LVX C3245
always send +3 V clock levels to the AD9801/AD9802.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9803 | CCD And Video Signal Processor For Electronic Cameras(電子照相機的CCD信號和視頻信號處理器) |
| AD9805 | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9805JS | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9807 | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9807JS | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9802JST | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9802JSTRL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD9803 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor For Electronic Cameras |
| AD9803JST | 制造商:Rochester Electronics LLC 功能描述: |
| AD9803JST-28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。