參數(shù)資料
型號: AD9801
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: CCD Signal Processor For Electronic Cameras(用于電子照相機的CCD信號處理器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: PLASTIC, TQFP-48
文件頁數(shù): 4/12頁
文件大?。?/td> 265K
代理商: AD9801
AD9801
–4–
REV. 0
Pin No.
Pin Name
Type
Description
1
2–11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
ADVSS
D0–D9
DRVDD
DRVSS
DSUBST
DVSS
ADCCLK
DVDD
STBY
PBLK
CLPOB
SHP
SHD
CLPDM
DVSS
CCDBYP2
DIN
PIN
CCDBYP1
PGACONT1
PGACONT2
ACVSS
CLAMP_BIAS
ACVDD
ACVDD
ACVDD
INT_BIAS1
CMLEVEL
INT_BIAS2
MODE2
MODE1
ADVSS
ADVDD
ADVDD
ADVSS
ADVSS
SUBST
VRB
VRT
P
DO
P
P
P
P
DI
P
DI
DI
DI
DI
DI
DI
DI
AO
AI
AI
AO
AI
AI
P
AO
P
AI
AI
AO
AO
AO
DI
DI
P
P
P
P
P
P
AO
AO
Analog Ground
Digital Data Outputs
+3 V Digital Driver Supply
Digital Driver Ground
Digital Substrate
Digital Ground
ADC Sample Clock Input
+3 V Digital Supply
Power down (Active HIGH)
Pixel Blanking (Active LOW)
Black Level Restore Clamp (Active LOW)
Reference Sample Clock Input
Data Sample Clock Input
Input Clamp (Active Low)
Digital Ground
CCD Bypass (Decouple to Analog Ground Through 0.1
μ
F)
CDS Input (Tie to Pin 27 and AC-Couple to CCD Output Through 0.1
μ
F)
CDS Input (See Above)
CCD Bypass (Decouple to Analog Ground Through 0.1
μ
F)
Coarse PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1
μ
F)
Fine PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1
μ
F)
Analog Ground
Clamp Bias Level (Decouple to Analog Ground Through 0.1
μ
F)
+3 V Analog Supply
+3 V Analog Supply
+3 V Analog Supply
Internal Bias Level (Decouple to Analog Ground Through 0.1
μ
F)
Common-Mode Level (Decouple to Analog Ground Through 0.1
μ
F)
Internal Bias Level (Decouple to Analog Ground Through 0.1
μ
F)
ADC Test Mode Control (See Digital Output Data Control)
ADC Test Mode Control (See Digital Output Data Control)
Analog Ground
+3 V Analog Supply
+3 V Analog Supply
Analog Ground
Analog Ground
Substrate (Connect to Analog Ground)
Bottom Reference Bypass (Decouple to Analog Ground Through 0.1
μ
F)
Top Reference Bypass (Decouple to Analog Ground Through 0.1
μ
F)
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10 11 12
36 35 34 33 32
27 26 25
31 30 29 28
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD9801
VRT
VRB
SUBST
ADVSS
ADVSS
ADVDD
ADVDD
ADVSS
MODE1
MODE2
INT_BIAS2
CMLEVEL
DRVSS
DSUBST
DVSS
ADCCLK
I
DVDD
STBY
PBLK
CLPOB
SHP
SHD
CLPDM
DVSS
A
A
A
C
A
P
P
C
P
D
C
A
(
D
D
D
D
D
D
D
D
(
D
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