參數(shù)資料
型號(hào)： AD9786BSV
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing
中文描述： PARALLEL, WORD INPUT LOADING, 16-BIT DAC, PQFP80
封裝： PLASTIC, MS-026-ADD, TQFP-80
文件頁(yè)數(shù)： 45/60頁(yè)
文件大小： 1497K
代理商： AD9786BSV
AD9786
OPERATING THE AD9786 REV F EVALUATION BOARD
This section helps the user get started with the AD9786
evaluation board. Because it is intended to provide starter
information to power up the board and verify correct operation,
a description of some of the more advanced modes of operation
has been omitted.
Rev. 0 | Page 45 of 60
POWER SUPPLIES
The AD9786 Rev F Evaluation Board has five power supply
connectors, labeled AVDD1, AVDD2, (ACVDD, ADVDD),
CLKVDD, and DVDD. The AD9786 itself actually has seven
power supply domains. To reconcile the power supply domains
on the chip with the power supply connectors on the evaluation
board, use Table 38.
Additionally, the DRVDD power supply on the AD9786 is used
to supply power for the digital input bus. DRVDD can be run
from 2.5 V or 3.3 V. On the evaluation board, DRVDD is jumper
selectable by JP1, just to the left of the chip on the evaluation
board. With the jumper set to the 3.3 V position, DRVDD chip
receives its power from VDD3IN. With the jumper set to the
2.5 V position, DRVDD receives its power from AVDIN.
PECL CLOCK DRIVER
The AD9786 system clock is driven from an external source via
connector S1. The AD9786 Evaluation Board includes an
OnSemiconductor MC100EPT22 PECL clock driver. In the
factory, the evaluation board is set to use this PECL driver as a
single-ended-to-differential clock receiver. The PECL driver can
be set to run from 2.5 V from the CLKVDD power connector,
or 3.3 V from the VDD3IN power connector. This setting is
done via jumper, JP2, situated next to the CLKVDD power
connector, and by setting input bias resistors R23 and R4 on the
evaluation board. The factory default is for the PECL driver to
be powered from CLKVDD at 2.5 V (R23 = 90.9 , R4 =
115 ). To operate the PECL driver with a 3.3 V supply, R23
must be replaced with a 115 resistor and R4 must be replaced
with a 90.9 resistor, as well as changing the position of JP2.
The schematic of the PECL driver section of the evaluation
board is shown in Figure 85. A low jitter sine wave should be
used as the clock source. Care must be taken to make sure the
clock amplitude does not exceed the power supply rails for the
PECL driver.
0
U2
7
1
2
COND;5
CLKVDDS;8
C32
0.1
μ
F
R23
115
R4
90.9
ACLKX
CLKVDDS
R5
50
R7
50
R6
50
CLKVDDS
MC100EPT22
CLK+
CLK–
Figure 85. PECL Driver on AD9786 Rev E Evaluation Board
Table 38.
Evaluation Board Label/
PS Domain on Chip
DVDD
CLKVDD
(ACVDD ADVDD)
AVDD2
AVDD1
Nominal Power
Supply Voltage (V)
2.5
2.5
2.5
3.3
3.3
Description
SPI port
Clock circuitry
Analog circuitry containing clock and digital interface circuitry
Switching analog circuitry
Analog output circuitry
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