參數(shù)資料
型號： AD9783BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 18/32頁
文件大?。?/td> 0K
描述： IC DAC 16BT 500MSPS LVDS 72LFCSP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 1
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 315mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應商設(shè)備封裝： 72-LFCSP-VQ（10x10）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 600M
Data Sheet
AD9780/AD9781/AD9783
Rev. B | Page 25 of 32
PARALLEL DATA PORT INTERFACE
The parallel port data interface consists of up to 18 differential
signals, DCO, DCI, and up to 16 data lines (D[15:0]), as shown
in Figure 56. DCO is the output clock generated by the AD9780/
AD9781/AD9783 that is used to clock out the data from the
digital data engine. The data lines transmit the multiplexed
I and Q data words for the I and Q DACs, respectively. DCI
provides timing information about the parallel data and signals
the I/Q status of the data.
As diagrammed in Figure 56, the incoming LVDS data is
latched by an internally generated clock referred to as the data
sampling signal (DSS). DSS is a delayed version of the main
DAC clock signal, CLKP/CLKN. Optimal positioning of the
rising and falling edges of DSS with respect to the incoming
data signals results in the most robust transmission of the DAC
data. Positioning the edges of DSS with respect to the data
signals is achieved by selecting the value of a programmable
delay element, SMP. A procedure for determining the optimal
value of SMP is given in the Optimizing the Parallel Port
Timing section.
In addition to properly positioning the DSS edges, maximizing
the opening of the eye in the clock input (DCIP/DCIN) and
data signals improves the reliability of the data port interface.
The two sources of degradation that reduce the eye in the clock
input and data signals are the jitter on these signals and the
skew between them. Therefore, it is recommended that the clock
input signals be generated in the same manner as the data
signals with the same output driver and data line routing. In
other words, it should be implemented as a 17th data line with
an alternating (010101 …) bit sequence.
FF
D15:D0
FF
SET_DLY
HLD_DLY
SMP_DLY
SEEK
CLK
DSS
DDSS
DDCI
RETIMING
AND
DEMUX
I DAC
Q DAC
06936-
071
CLOCK
DISTRIBUTION
DCIP/DCIN
DCOP/DCON
Figure 56. Digital Data Port Block Diagram
OPTIMIZING THE PARALLEL PORT TIMING
Before outlining the procedure for determining the delay for
SMP (that is, the positioning of DSS with respect to the data
signals), it is worthwhile to describe the simplified block
diagram of the digital data port. As can be seen in Figure 57, the
data signals are sampled on the rising and falling edges of DSS.
From there, the data is demultiplexed and retimed before being
sent to the DACs.
The clock input signal provides timing information about the
parallel data, as well as indicating the destination (that is, I DAC
or Q DAC) of the data. A delayed version of DCI is generated
by a delay element, SET, and is referred to as DDCI. DDCI is
sampled by a delayed version of the DSS signal, labeled as DDSS
in Figure 56. DDSS is simply DSS delayed by a period of time,
HLD. The pair of delays, SET and HLD, allows accurate timing
information to be extracted from the clock input. Increasing the
delay of the HLD block results in the clock input being sampled
later in its cycle. Increasing the delay of the SET block results in
the clock input being sampled earlier in its cycle. The result of
this sampling is stored and can be queried by reading the SEEK
bit. Because DSS and the clock input signal are the same
frequency, the SEEK bit should be a constant value. By varying
the SET and HLD delay blocks and seeing the effect on the
SEEK bit, the setup-and-hold timing of DSS with respect to
clock input (and, hence, data) can be measured.
I0
Q0
I1
Q1
I2
Q2
SAMPLE 6
SAMPLE 5
SAMPLE 4
SAMPLE 3
SAMPLE 2
SAMPLE 1
tHLD0
DATA
DCIP/DCIN
DSS
06936-
072
tHLD0
Figure 57. Timing Diagram of Parallel Interface
The incremental units of SET, HLD, and SMP are in units of
real time, not fractions of a clock cycle. The nominal step size
for SET and HLD is 80 ps. The nominal step size for SMP is
160 ps. Note that the value of SMP refers to Register 0x05,
Bits[4:0], SET refers to Register 0x04, Bits[7:4], and HLD refers
to Register 0x04, Bits[3:0].
A procedure for configuring the device to ensure valid sampling
of the data signals follows. Generally speaking, the procedure
begins by building an array of setup-and-hold values as the sample
delay is swept through a range of values. Based on this infor-
mation, a value of SMP is programmed to establish an optimal
sampling point. This new sampling point is then double-checked
to verify that it is optimally set.
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AD9783BCPZRL 功能描述:IC DAC 16BT 500MSPS LVDS 72LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
AD9783-DPG2-EBZ 功能描述:BOARD EVAL FOR AD9783 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9783-DUAL-EBZ 制造商:Analog Devices 功能描述:DUAL 16B, 500 MSPS LVDS DAC - Boxed Product (Development Kits)
AD9783-EBZ 制造商:Analog Devices 功能描述:DUAL 16B, 600 MSPS LVDS DAC - Bulk
AD9784 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 200 MSPS/500 MSPS TxDAC+ with 2×/4×/8× Interpolation and Signal Processing
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