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參數(shù)資料
| 型號： | AD9781BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BT 500MSPS LVDS 72LFCSP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 315mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 72-LFCSP |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 600M |
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AD9780/AD9781/AD9783
Data Sheet
Rev. B | Page 26 of 32
Building the Array
The following procedure is used to build the array:
1. Set the values of SMP, SET, and HLD to 0. Read and record
the value of the SEEK bit.
2. With SMP and SET set to 0, increment the HLD value until
the SEEK bit toggles, and then record the HLD value. This
measures the hold time as shown in Figure 57.
3. With SMP and HLD set to 0, increment the SET value until
the SEEK bit toggles, and then record the SET value. This
measures the setup time as shown in Figure 57.
4. Set the value of SET and HLD to 0. Increment the value of
SMP and record the value of the SEEK bit.
5. Increment HLD until the SEEK bit toggles, and then record
the HLD value. Set HLD to 0 and increment SET until the
SEEK bit toggles, and then record the SET value.
6. Repeat Step 4 and Step 5 until the procedure has been
completed for SMP values from 0 to 31.
Note that while building the table, a value for either SET or
HLD may not be found to make the SEEK bit toggle. In this
case, assume a value of 15.
Table 14. Timing Data Arrays
fDACCLK = 200 MHz
fDACCLK = 400 MHz
fDACCLK = 500 MHz
SMP
SEEK
SET
HLD
SEEK
SET
HLD
SEEK
SET
HLD
0
6
15
0
2
13
0
11
1
0
8
15
0
4
11
0
2
9
2
0
10
15
0
6
9
0
3
7
3
0
12
15
0
8
7
0
5
4
0
15
0
10
4
0
8
2
5
0
15
13
0
12
2
0
10
1
6
0
15
11
0
14
1
9
7
0
15
9
1
13
1
2
7
8
0
15
7
1
3
11
1
4
9
0
15
5
1
4
9
1
7
2
10
0
15
3
1
6
7
1
9
1
11
0
15
1
8
5
0
1
10
12
0
15
0
1
10
3
0
2
8
13
1
15
1
12
1
0
4
7
14
1
4
15
0
15
0
6
4
15
1
6
15
0
2
13
0
9
2
16
1
8
15
0
4
11
0
11
0
17
1
10
15
0
6
9
1
8
18
1
12
15
0
7
1
3
7
19
1
13
15
0
9
5
1
5
20
1
15
13
0
11
3
1
7
2
21
1
15
11
0
13
1
9
1
22
1
15
9
0
15
0
1
10
23
1
15
7
1
2
11
0
2
8
24
1
15
5
1
4
9
0
4
6
25
1
15
3
1
6
7
0
7
4
26
1
15
1
8
5
0
9
2
27
1
15
0
1
9
3
0
10
0
28
0
1
15
1
11
2
1
8
29
0
1
15
1
11
2
1
8
30
0
1
15
1
11
2
1
8
31
0
1
15
1
11
2
1
8
Table 14 shows example arrays taken at DAC sample rates of
200 MHz, 400 MHz, and 500 MHz. It should be noted that the
delay from the DCO input to the DCI output of the data source
has a profound effect on when the SEEK bit toggles over the
range of SMP values. Therefore, the tables generated in any
particular system do not necessarily match the example timing
data arrays in Table 14.
As may be seen in Table 14, at 500 MHz the device has only two
working SMP settings. There is no way to monitor timing
margin in real time, so the output must be interrupted to check
or correct timing errors. The device should therefore not be
clocked above 500 MHz in applications where 100% up time is a
requirement.
Determining the SMP Value
Once the timing data array has been built, the value of SMP can
be determined using the following procedure:
1. Look for the SMP value that corresponds to the 0-to-1
transition of the SEEK bit in the table. In the 500 MHz case
from Table 14, this occurs for an SMP value of 6.
2. Look for the SMP value that corresponds to the 1-to-0
transition of the SEEK bit in the table. In the 500 MHz case
from Table 14, this occurs for an SMP value of 11.
3. The same two values found in Step 1 and Step 2 indicate
the valid sampling window. In the 500 MHz case, this
occurs for an SMP value of 11.
4. The optimal SMP value in the valid sampling window is
where the following two conditions are true: SET < HLD
and |HLD SET| is the smallest value.
In the 500 MHz case, the optimal SMP value is 7.
After programming the calculated value of SMP (referred to as
SMPOPTIMAL), the configuration should be tested to verify that
there is sufficient timing margin. This can be accomplished by
ensuring that the SEEK bit reads back as a 1 for SMP values
equal to SMPOPTIMAL + 1 and SMPOPTIMAL 1. Also, it should be
noted that the sum of SET and HLD should be a minimum of 8.
If the sum is lower than this, you should check for excessive jitter
on the clock input line and check that the frequency of the clock
input does not exceed the data sheet maximum of 500 MHz (or
1000 Mbps).
As mentioned previously, low jitter and skew between the input
data bits and DCI are critical for reliable operation at the maxi-
mum input data rates. Figure 58 shows the eye diagram for the
input data signals that were used to collect the data in Table 14.
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