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參數(shù)資料
| 型號： | AD977BRRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 100KSPS 20-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 3 個單端，單極；3 個單端，雙極 |
| 配用： | EVAL-AD977CB-ND - BOARD EVAL FOR AD977 EVAL-AD977ACB-ND - BOARD EVAL FOR AD977A |
AD977/AD977A
–10–
REV. D
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION NO SYNC OUTPUT
GENERATED
Figure 5 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, without the generation of a SYNC out-
put. After a conversion is initiated, indicated by
BUSY going
low, the result of the previous conversion can be read while
CS
is low and R/
C is high. In this mode CS can be tied low. The
MSB will be valid on the 1st falling edge and the 2nd rising
edge of DATACLK. The LSB will be valid on the 16th falling
edge and the 17th rising edge of DATACLK. A minimum of 16
clock pulses are required for DATACLK if the receiving device
will be latching data on the falling edge of DATACLK. A mini-
mum of 17 clock pulses are required for DATACLK if the
receiving device will be latching data on the rising edge of
DATACLK. Approximately 40 ns after the 17th rising edge of
DATACLK (if provided) the DATA output pin will reflect the
state of the TAG input pin during the first rising edge of
DATACLK.
For both the AD977 and the AD977A the data should be
clocked out during the first half of
BUSY so not to degrade
conversion performance. For the AD977 this requires use of a
4.8 MHz DATACLK or greater with data being read out as
soon as the conversion process begins. For the AD977A it
requires use of a 10 MHz DATACLK or greater.
It is not recommended that data be shifted through the TAG
input in this mode as it will certainly result in clocking of data
during the second half of the conversion.
EXTERNAL DISCONTINUOUS CLOCK DATA READ
AFTER CONVERSION WITH SYNC OUTPUT GENERATED
Figure 6 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either
CS is high or while both CS and R/C
are low. After a conversion is complete, indicated by
BUSY
returning high, the result of that conversion can be read while
CS is Low and R/C is high. In this mode CS can be tied low. In
Figure 6 clock pulse #0 is used to enable the generation of a
SYNC pulse. The SYNC pulse is actually clocked out approxi-
mately 40 ns after the rising edge of clock pulse #1. The SYNC
pulse will be valid on the falling edge of clock pulse #1 and the
rising edge of clock pulse #2. The MSB will be valid on the
falling edge of clock pulse #2 and the rising edge of clock pulse
#3. The LSB will be valid on the falling edge of clock pulse #17
and the rising edge of clock pulse #18. Approximately 40 ns
after the rising edge of clock pulse #18 the DATA output pin
will reflect the state of the TAG input pin during the rising edge
of clock pulse #2. The advantage of this method of reading data
is that it is not being clocked out during a conversion and there-
fore conversion performance is not degraded.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz),
and with the AD977A, the maximum possible throughput is
approximately 195 kHz and not the rated 200 kHz.
For details on use of the TAG input with this mode see the Use
of the TAG Input section.
R/C
BUSY
EXT
DATACLK
t13
t15
BIT 15
(MSB)
BIT 14
12
DATA
SYNC
t14
t12
015
16
t22
BIT 0
(LSB)
t18
t1
t21
t2
t18
t20
Figure 5. Conversion and Read Timing for Reading Previous Conversion Results During A Conversion Using External
Discontinuous Data Clock (EXT/
INT Set to Logic High, CS Set to Logic Low)
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