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參數(shù)資料
| 型號： | AD977AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converter |
| 中文描述： | 3-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 284K |
| 代理商： | AD977AN |
AD977/AD977A
–6–
REV. D
PIN FUNCTION DESCRIPTIONS
Pin No.
DIP/SOIC
Pin No.
SSOP
Mnemonic
Description
1, 3, 4
2
5
1, 3, 4
2
6
R1
IN
, R2
IN
, R3
IN
AGND1
CAP
Analog Input. Refer to Table I, Table II for input range configuration.
Analog Ground. Used as the ground reference point for the REF pin.
Reference buffer output. Connect a 2.2
μ
F tantalum capacitor between CAP and
Analog Ground.
Reference Input/Output. The internal 2.5 V reference is available at this pin.
Alternatively an external reference can be used to override the internal reference. In
either case, connect a 2.2
μ
F tantalum capacitor between REF and Analog Ground.
Analog Ground.
This digital input is used to select the data format of a conversion result. With SB/
BTC
tied LOW, conversion data will be output in Binary Two’s Complement format. With
SB/
BTC
connected to a logic HIGH, data is output in Straight Binary format.
Digital select input for choosing the internal or an external data clock. With EXT/
INT
tied LOW, after initiating a conversion, 16 DATACLK pulses transmit the previous
conversion result as shown in Figure 3. With EXT/
INT
set to a logic HIGH, output
data is synchronized to an external clock signal connected to the DATACLK input.
Data is output as indicated in Figure 4 through Figure 9.
Digital Ground.
Digital output frame synchronization for use with an external data clock
(EXT/
INT
= Logic HIGH). When a read sequence is initiated, a pulse one
DATACLK period wide is output synchronous to the external data clock.
Serial data clock input or output, dependent upon the logic state of the EXT/
INT
pin. When using the internal data clock (EXT/
INT
= Logic LOW), a conversion
start sequence will initiate transmission of 16 DATACLK periods. Output data is
synchronous to this clock and is valid on both its rising and falling edges (Figure 3).
When using an external data clock (EXT/
INT
= Logic HIGH), the
CS
and R/
C
signals control how conversion data is accessed.
The serial data output is synchronized to DATACLK. Conversion results are
stored in an on-chip register. The AD977 provides the conversion result, MSB first,
from its internal shift register. The DATA format is determined by the logic level of
SB/
BTC
. When using the internal data clock (EXT/
INT
= Logic LOW), DATA is
valid on both the rising and falling edges of DATACLK. Between conversions
DATA will remain at the level of the TAG input when the conversion was started.
Using an external data clock (EXT/
INT
= Logic HIGH) allows previous conversion
data to be accessed during a conversion (Figures 5, 7 and 9) or the conversion
result can be accessed after the completion of a conversion (Figures 4, 6 and 8).
This digital input can be used with an external data clock, (EXT/
INT
= Logic
HIGH) to daisy chain the conversion results from two or more AD977s onto a
single DATA line. The digital data level on TAG is output on DATA with a delay
of 16 or 17 external DATACLK periods after the initiation of the read sequence.
Dependent on whether a SYNC is not present or present.
Read/Convert Input. Is used to control the conversion and read modes of the
AD977. With
CS
LOW; a falling edge on R/
C
holds the analog input signal inter-
nally and starts a conversion, a rising edge enables the transmission of the conver-
sion result.
Chip Select Input. With R/
C
LOW, a falling edge on
CS
will initiate a conversion.
With R/
C
HIGH, a falling edge on
CS
will enable the serial data output sequence.
Busy Output. Goes LOW when a conversion is started, and remains LOW until the
conversion is completed and the data is latched into the on-chip shift register.
Power-Down Input. When set to a logic HIGH power consumption is reduced and
conversions are inhibited. The conversion result from the previous conversion is
stored in the onboard shift register.
Analog Power Supply. Nominally 5 V.
Digital Power Supply. Nominally 5 V.
6
7
REF
7
8
9
12
AGND2
SB/
BTC
9
13
EXT/
INT
10
11
14
15
DGND
SYNC
12
16
DATACLK
13
17
DATA
14
19
TAG
15
21
R/
C
16
24
CS
17
25
BUSY
18
26
PWRD
19
20
27
28
V
ANA
V
DIG
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| AD977AR | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converter |
| AD977ARS | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converter |
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|---|---|
| AD977ANZ | 功能描述:IC ADC 16BIT 100KSPS 20-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD977AR | 功能描述:IC ADC 16BIT 100KSPS 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD977AR-REEL | 功能描述:IC ADC 16BIT 100KSPS 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD977ARS | 功能描述:IC ADC 16BIT 100KSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD977ARSRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Serial 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:IC, MONO 16-BIT ADC - Bulk |
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