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參數(shù)資料
| 型號： | AD977ABRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converter |
| 中文描述： | 3-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 284K |
| 代理商： | AD977ABRS |
AD977/AD977A
–11–
REV. D
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION WITH SYNC OUTPUT
GENERATED
Figure 7 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either
CS
is High or while both
CS
and R/
C
are low. In Figure 7 a conversion is initiated by taking R/
C
low
with
CS
tied low. While this condition exists a transition of
DATACLK, clock pulse #0, will enable the generation of a
SYNC pulse. Less then 83 ns after R/
C
is taken low the
BUSY
output will go low to indicate that the conversion process has
began. Figure 7 shows R/
C
then going high and after a delay of
greater than 15 ns (t
15
) clock pulse #1 can be taken high to
request the SYNC output. The SYNC output will appear
approximately 40 ns after this rising edge and will be valid on
the falling edge of clock pulse #1 and the rising edge of clock
pulse #2. The MSB will be valid approximately 40 ns after the
rising edge of clock pulse #2 and can be latched off either the
falling edge of clock pulse #2 or the rising edge of clock pulse
#3. The LSB will be valid on the falling edge of clock pulse #17
and the rising edge of clock pulse #18. Approximately 40 ns
after the rising edge of clock pulse #18, the DATA output
pin will reflect the state of the TAG input pin during the
rising edge of clock pulse #2.
BUSY
R/C
EXT
DATACLK
t
13
BIT 15
(MSB)
BIT 14
1
2
DATA
SYNC
t
14
t
12
0
3
17
18
t
2
t
17
BIT 0
(LSB)
TAG 0
TAG 1
TAG 0
TAG 1
TAG 2
TAG 16
TAG 17
TAG 18
t
18
TAG 19
TAG
TAG 2
4
t
15
t
15
t
15
t
12
t
18
t
24
t
23
Figure 6. Conversion and Read Timing Using An External Discontinuous Data Clock (EXT/
INT
Set to Logic High,
CS
Set
to Logic Low)
BUSY
R/C
EXT
DATACLK
t
13
t
15
BIT 15
(MSB)
BIT 14
1
2
DATA
SYNC
t
14
t
12
0
3
18
t
1
t
12
BIT 0
(LSB)
TAG 0
t
22
t
15
t
20
t
2
t
17
t
18
t
18
Figure 7. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using External
Discontinuous Data Clock (EXT/
INT
Set to Logic High,
CS
Set to Logic Low)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD977ABRSRL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 16-bit Serial 28-Pin SSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 200KSPS 16BIT SERL 28SSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:200 KSPS 16 BIT ADC - Tape and Reel |
| AD977ABRSZ | 功能描述:IC ADC 16BIT 200KSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD977ABRSZRL | 功能描述:IC ADC 16BIT 200KSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD977ABRZ | 功能描述:IC ADC 16BIT 200KSPS 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD977ACN | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 16-bit Serial 20-Pin PDIP N 制造商:Rochester Electronics LLC 功能描述:200 KSPS 16-BIT ADC - Bulk |
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