- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8569 > AD9778BSVZRL (Analog Devices Inc)IC DAC 14BIT DUAL 1GSPS 100TQFP PDF資料下載
參數(shù)資料
| 型號： | AD9778BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT DUAL 1GSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 1G |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
AD9776/AD9778/AD9779
Rev. A | Page 26 of 56
For multibyte transfers, this address is the starting byte address.
The remaining register addresses are generated by the device
based on the LSB-first bit (Register 0x00, Bit 6).
Table 10. Byte Transfer Count
N1
N0
Description
0
Transfer one byte
0
1
Transfer three bytes
1
0
Transfer two bytes
1
Transfer four bytes
Serial Interface Port Pin Descriptions
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device
and to run the internal state machines. The maximum frequency
of SCLK is 40 MHz. All data input is registered on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should
stay low during the entire communication cycle.
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However, this
pin can be used as a bidirectional data line. The configuration
of this pin is controlled by Register 0x00, Bit 7. The default is
Logic 0, configuring the SDIO pin as unidirectional.
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the device
operates in a single bidirectional I/O mode, this pin does not
output data and is set to a high impedance state.
MSB/LSB TRANSFERS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register Bit LSB_FIRST
(Register 0x00, Bit 6). The default is MSB-first (LSB-first = 0).
When LSB-first = 0 (MSB-first) the instruction and data bit
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent data
bytes should follow from high address to low address. In MSB-first
mode, the serial port internal byte address generator decrements
for each data byte of the multibyte communication cycle.
When LSB-first = 1 (LSB-first) the instruction and data bit
must be written from LSB to MSB. Multibyte data transfers in
LSB-first format start with an instruction byte that includes the
register address of the least significant data byte followed by mul-
tiple data bytes. The serial port internal byte address generator
increments for each byte of the multibyte communication cycle.
The serial port controller data address decrements from the
data address written toward 0x00 for multibyte I/O operations if
the MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x1F for
multibyte I/O operations if the LSB-first mode is active.
R/W N1 N0
A4 A3
A2 A1 A0 D7 D6N D5N
D00
D10
D20
D30
D7 D6N D5N
D00
D10
D20
D30
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
05
36
1-
0
50
Figure 53. Serial Register Interface Timing MSB-First
A0 A1 A2 A3 A4
N0 N1 R/W D00 D10 D20
D7N
D6N
D5N
D4N
D00 D10 D20
D7N
D6N
D5N
D4N
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
05
36
1-
0
51
Figure 54. Serial Register Interface Timing LSB-First
INSTRUCTION BIT 6
INSTRUCTION BIT 7
CSB
SCLK
SDIO
tDS
tDH
tPWH
tPWL
tSCLK
05361-052
Figure 55. Timing Diagram for SPI Register Write
DATA BIT n–1
DATA BIT n
CSB
SCLK
SDIO
SDO
tDV
05361-053
Figure 56. Timing Diagram for SPI Register Read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-2N2-IV | CONVERTER MOD DC/DC 15V 150W |
| VE-2N0-IV | CONVERTER MOD DC/DC 5V 150W |
| VE-B34-MU | CONVERTER MOD DC/DC 48V 200W |
| VI-23R-IV | CONVERTER MOD DC/DC 7.5V 150W |
| VI-23P-IV | CONVERTER MOD DC/DC 13.8V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9778BSVZRL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters |
| AD9778-EB | 制造商:Analog Devices 功能描述:EVAL BOARD 14-BIT DUAL INTERPOLATION DAC - Bulk |
| AD9778-EBZ | 制造商:Analog Devices 功能描述: |
| AD9779 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MHz to 6 GHz Broadband Quadrature Modulator |
| AD9779A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。