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參數(shù)資料
| 型號(hào)： | AD9774EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation Filters |
| 中文描述： | 14位，32 MSPS的TxDAC系列⑩4倍內(nèi)插濾波器 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 313K |
| 代理商： | AD9774EB |
AD9774
–6–
REV. B
PIN FUNCTION DESCRIPTIONS
Pin No.
1, 19, 40, 44
2
3–14
15
16, 17, 42
18, 41
20
Name
DCOM
DB13
DB12–DB1
DB0
NC
DVDD
CLK IN/OUT
Description
Digital Common.
Most Significant Data Bit (MSB).
Data Bits 1–12.
Least Significant Data Bit (LSB).
No Internal Connection.
Digital Supply Voltage (+2.7 V to +5.5 V).
Clock Input when PLL Clock Multiplier enabled. Clock Output when PLL Clock Multiplier
disabled. Data latched on rising edge.
Phase Lock Loop Lock Signal. Active High indicates PLL is locked to input clock.
External 4
×
Clock Input when PLL is disabled. No Connect when internal PLL is active.
PLL Range Control Pin. Connect to PLLCOM if CLKIN is above 10 MSPS. Connect to
PLLVDD if CLKIN is between 10 MSPS and 5.5 MSPS.
Internal Voltage Controlled Oscillator (VCO) Enable/Disable Pin. Connect to PLLVDD to enable
VCO. Connect to PLLCOM to disable VCO and drive CLK4
×
IN with external VCO output.
PLL Loop Filter Node. Connect to
externa
l VCO control input if
internal
VCO disabled.
Phase Lock Loop (PLL) Supply Voltage (+2.7 V to +5.5 V). Must be set to similar voltage as DVDD.
Phase Lock Loop Common.
Phase Lock Loop Enable. Connect to PLLVDD to enable. Connect to PLLCOM to disable.
Factory Test. Leave Open.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO
to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to
ACOM). Requires 0.1
μ
F capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
Noise Reduction Node. Add 0.1
μ
F to AVDD.
Analog Common.
Analog Supply Voltage (+2.7 V to +5.5 V).
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Internal bias node for switch driver circuitry. Decouple to ACOM with 0.1
μ
F capacitor.
Power-Down Control Input. Active High. Connect to DCOM if not used.
SNOOZE Control Input. Deactivates 4
×
interpolation filter to reduce digital power consumption
only. Active High. Connect to DCOM if not used.
21
22
23
PLLLOCK
CLK4
×
IN
PLLDIVIDE
24
VCO IN/EXT
25
26
27
28
29
30
LPF
PLLVDD
PLLCOM
PLLENABLE
UNUSED
REFLO
31
REFIO
32
33
34
35
36
37
38
39
43
FSADJ
REFCOMP
ACOM
AVDD
IOUTB
IOUTA
ICOMP
SLEEP
SNOOZE
PIN CONFIGURATION
3
4
5
6
7
1
2
10
11
8
9
40 39 38
41
42
43
44
36 35 34
37
29
30
31
32
33
27
28
25
26
23
24
PIN 1
TOP VIEW
(Not to Scale)
12 13 14 15 16 17 18 19 20 21 22
REFCOMP
FSADJ
REFIO
REFLO
UNUSED
PLLENABLE
PLLCOM
AD9774
DCOM
DB13
DB12
DB11
DB10
DB9
DB8
NC = NO CONNECT
DB7
DB6
DB5
DB4
PLLVDD
LPF
VCO IN/EXT
PLLDIVIDE
D
D
D
D
N
N
D
D
C
P
C
3
I
I
A
D
S
D
I
A
D
S
I
N
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9774 | 14-Bit，32 MSPS DAC with 4× Interpolation Filters(14位的，輸入數(shù)據(jù)數(shù)率為32MSPS的具有內(nèi)插濾波器的D/A轉(zhuǎn)換器) |
| AD9775 | 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter |
| AD9775BSV | 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter |
| AD9775EB | 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter |
| AD9777 | 16-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9774-EB | 制造商:Analog Devices 功能描述: |
| AD9774-EBZ | 制造商:Analog Devices 功能描述:14-BIT 32 MSPS TXDAC W/4X INTERPOLATION - Bulk |
| AD9775 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter |
| AD9775BSV | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 14-bit 80-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:14BIT 160 MSPS DUAL TXDAC+ D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:IC 14-BIT DAC |
| AD9775BSVRL | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 14-bit 80-Pin TQFP EP T/R |
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