- 您現(xiàn)在的位置：買賣IC網 > PDF目錄362116 > AD976CRS (ANALOG DEVICES INC) 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters PDF資料下載
參數資料
| 型號： | AD976CRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數： | 11/23頁 |
| 文件大小： | 577K |
| 代理商： | AD976CRS |
AD9761
–11–
an analog filter following the DAC. The complexity of this ana-
log filter is typically determined by the proximity of the desired
fundamental to the first image and the required amount of
image suppression.
Referring to Figure 23, the “new” first image associated with the
DAC’s higher data rate
after
interpolation is “pushed” out fur-
ther relative to the input signal. The “old” first image associated
with the lower DAC data rate
before
interpolation is suppressed
by the digital filter. As a result, the transition band for the ana-
log reconstruction filter is increased thus reducing the complex-
ity of the analog filter.
The digital interpolation filters for I and Q paths are identical
43 tap halfband symmetric FIR filters. Each filter receives
deinterleaved I or Q data from the digital input interface. The
input CLOCK signal is internally divided by two to generate the
filter clock. The filters are implemented with two parallel paths
running at the filter clock rate. The output from each path is
selected on opposite phases of the filter clock, thus producing
interpolated filtered output data at the input clock rate. The
frequency response and impulse response of these filters are
shown in Figures 2a and 2b. Table I lists the idealized filter
coefficients that correspond to the filter’s impulse response.
The digital section of the AD9761 also includes an input inter-
face section designed to support interleaved I and Q input data
from a single 10-bit bus. This section de-interleaves the I and Q
input data while ensuring its proper pairing for the 2
×
interpola-
tion filters. A SLEEP/RESET input serves a dual function by
providing a reset function for this section as well as providing
power down functionality. Refer to the DIGITAL INPUT AND
INTERFACE CONSIDERATIONS and SLEEP/RESET
sections for a more detailed discussion.
DAC TRANSFER FUNCTION
Each I and Q DAC provides complementary current output
pins: IOUT(A/B) and QOUT(A/B) respectively. Note, QOUTA
and QOUTB operate identically to IOUTA and IOUTB. IOUTA
will provide a near full-scale current output, I
OUTFS
, when all
bits are high (i.e., DAC CODE = 1023) while IOUTB, the
complementary output, provides no current. The current output
of IOUTA and IOUTB are a function of both the input code
and I
OUTFS
and can be expressed as:
I
IOUTA
= (
DAC CODE
/1024)
×
I
OUTFS
(1)
I
IOUTB
= (1023 –
DAC CODE
)/1024
×
I
OUTFS
where:
DAC CODE
= 0 to 1023 (i.e., Decimal Representation).
As previously mentioned, I
OUTFS
is a function of the reference
current, I
REF
, which is nominally set by a reference, V
REFIO
, and
external resistor, R
SET
. It can be expressed as:
I
OUTFS
= 16
×
I
REF
where:
I
REF
=
V
REFIO
/
R
SET
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
LOAD
, which are tied to analog common, ACOM. Note,
R
LOAD
represents the equivalent load resistance seen by IOUTA
(2)
(3)
(4)
or IOUTB. The single-ended voltage output appearing at IOUTA
and IOUTB pins is simply:
V
IOUTA
= I
IOUTA
×
R
LOAD
V
IOUTB
= I
IOUTB
×
R
LOAD
Note, the full-scale value of V
IOUTA
and V
IOUTB
should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, V
IDIFF
, appearing across IOUTA and
IOUTB is:
V
IDIFF
=(
I
IOUTA
– I
IOUTB
)
×
R
LOAD
Substituting the values of I
IOUTA
, I
IOUTB
, and I
REF
; V
IDIFF
can be
expressed as:
V
IDIFF
={(2
DAC CODE
– 1023)/1024)}
×
(16
R
LOAD
/R
SET
)
×
V
REFIO
These last two equations highlight some of the advantages of
operating the AD9761 differentially. First, differential operation
will help cancel common-mode error sources associated with
I
IOUTA
and I
IOUTB
such as noise and distortion. Second, the differ-
ential code dependent current and subsequent voltage, V
IDIFF
, is
twice the value of the single-ended voltage output (i.e., V
IOUTA
or V
IOUTB
) thus providing twice the signal power to the load.
(5)
(6)
(7)
(8)
REFERENCE OPERATION
The AD9761 contains an internal 1.20 V bandgap reference
which can be easily disabled and overridden by an external
reference. REFIO serves as either an
input or output
depending
on whether the internal or an external reference is selected. If
REFLO is tied to ACOM as shown in Figure 24, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference must be filtered externally with
a ceramic chip capacitor of 0.1
μ
F or greater from REFIO to
REFLO. Also, REFIO should be buffered with an external
amplifier having a low input bias current (i.e., <1
μ
A) if any
additional loading is required.
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO
COMP2
AVDD
0.1 F
R
SET
2k
0.1 F
OPTIONAL EXTERNAL
REF BUFFER FOR
ADDITIONAL LOADS
COMPENSATION
CAPACITOR
REQUIRED
AD9761
Figure 24. Internal Reference Configuration
The internal reference can also be disabled by connecting REFLO
to AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 25. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1
μ
F compensation capacitor is not required
since the internal reference is disabled and the high input imped-
ance (i.e., 1 M
) of REFIO minimizes any loading of the
external reference
.
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關PDF資料 |
PDF描述 |
|---|---|
| AD9950KJ | Parallel-Input Frequency Synthesizer |
| AD9950TJ | Parallel-Input Frequency Synthesizer |
| AD9955KS-6 | RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS |
| AD9955KS-66 | Parallel-Input Frequency Synthesizer |
| AD9984A | 3-Phase, Buck Controllers for AMD CPUs; Package: QFN; No of Pins: 38; Temperature Range: 0°C to +70°C |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD976CRSZ | 功能描述:IC ADC 16BIT 100KSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD976CRZ | 功能描述:IC ADC 16BIT 100KSPS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD977 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converter |
| AD9772 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 150 MSPS TxDAC⑩ with 2x Interpolation Filter |
| AD9772A | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
發(fā)布緊急采購，3分鐘左右您將得到回復。