參數(shù)資料
型號(hào)： AD976CR
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters
中文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 10/23頁(yè)
文件大?。?/td> 577K
代理商： AD976CR
AD9761
–10–
REV. B
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9761. The
AD9761 is a complete dual channel, high speed, 10-bit CMOS
DAC capable of operating up to a 40 MHz clock rate. It has
been optimized for the transmit section of wideband communi-
cation systems employing I and Q modulation schemes. Excel-
lent matching characteristics between channels reduces the need
for any external calibration circuitry. Dual matching 2
×
interpo-
lation filters included in the I and Q data path simplify any post,
bandlimiting filter requirements. The AD9761 interfaces with a
single 10-bit digital input bus that supports interleaved I and Q
input data.
ACOM
REFLO
FSADJ
REFIO
"I"
IOUTA
IOUTB
WRITE INPUT
SELECT INPUT
DCOM
DVDD
CLOCK
AD9761
2
LATCH
"I"
REFERENCE
COMP1
COMP2
COMP3
BIAS
GENERATOR
QOUTA
QOUTB
2
LATCH
"Q"
CMUX
AVDD
DAC DATA
INPUTS
(10 BITS)
SLEEP
"Q"
Figure 22. Dual DAC Functional Block Diagram
Referring to Figure 22, the AD9761 consists of an analog section
and a digital section. The analog section includes matched I and Q
10-bit DACs, a 1.20 V bandgap voltage reference and a reference
control amplifier. The digital section includes: two 2
×
interpola-
tion filters; segment decoding logic; and some additional digital
input interface circuitry. The analog and digital sections of the
AD9761 have separate power supply inputs (i.e., AVDD and
DVDD) that can operate independently. The digital supply can
operate over a 2.7 V to 5.5 V range, allowing it to accommodate
TTL as well as 3.3 V and 5 V CMOS logic families. The analog
supply must be restricted from 3.0 V to 5.5 V to maintain
optimum performance.
Each DAC consists of a large PMOS current source array capable
of providing up to 10 mA of full-scale current, I
OUTFS
. Each
array is divided into 15 equal currents that make up the four
most significant bits (MSBs). The next four bits or middle bits
consist of 15 equal current sources whose value are 1/16th of an
MSB current source. The remaining LSBs are binary weighted
fractions of the middle-bits current sources. All of these current
sources are switched to one or the other of two output nodes (i.e.,
IOUTA or IOUTB) via PMOS differential current switches.
The full-scale output current, I
OUTFS
, of each DAC is regulated
from the same voltage reference and control amplifier, thus ensur-
ing excellent gain matching and drift characteristics between
DACs. I
OUTFS
can be set from 1 mA to 10 mA via an external
resistor, R
SET
. The external resistor in combination with both
the reference control amplifier and voltage reference, V
REFIO
,
sets the reference current, I
REF
, which is mirrored over to the
segmented current sources with the proper scaling factor. I
OUTFS
is exactly sixteen times the value of I
REF
.
The I and Q DACs are simultaneously updated on the rising
edge of CLOCK with digital data from their respective 2
×
digi-
tal interpolation filters. The 2
×
interpolation filters essentially
multiplies the input data rate of each DAC by a factor of two,
relative to its original input data rate while simultaneously reducing
the magnitude of first image associated with the DAC’s original
input data rate. Since the AD9761 supports a single 10-bit
digital bus with interleaved I and Q input data, the original I
and Q input data rate before interpolation is one-half the CLOCK
rate. After interpolation, the data rate into each I and Q DAC
becomes equal to the CLOCK rate.
The benefits of an interpolation filter are clearly seen in Figure
23, which shows an example of the frequency and time domain
representation of a discrete time sine wave signal before and
after it is applied to a digital interpolation filter. Images of the
sine wave signal appear around multiples of the DAC’s input
data rate as predicted by the sampling theory. These undesirable
images will also appear at the output of a reconstruction DAC,
although modified by the DAC’s sin(x)/(x) response. In many
bandlimited applications, these images must be suppressed by
FUNDAMENTAL
1
f
CLOCK
FUNDAMENTALFILTER
SU"OLD"
1
ST
IMAGE
"NEW"
f
CLOCK
1
ST
IMAGE
2
f
CLOCK
f
CLOCK
f
CLOCK
2
f
CLOCK
DACs"SX
TIME DOMAIN
FREQUENCY DOMAIN
2x INTERPOLATION FILTER
2x
INPUT DATA LATCH
DAC
f
CLOCK
f
CLOCK
2
f
CLOCK
2
f
CLOCK
2
Figure 23. Time and Frequency Domain Example of Digital Interpolation Filter
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料
PDF描述
AD976CRS 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters
AD9950KJ Parallel-Input Frequency Synthesizer
AD9950TJ Parallel-Input Frequency Synthesizer
AD9955KS-6 RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS
AD9955KS-66 Parallel-Input Frequency Synthesizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD976CRS 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:IC, MONO 16-BIT ADC - Bulk
AD976CRSZ 功能描述:IC ADC 16BIT 100KSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD976CRZ 功能描述:IC ADC 16BIT 100KSPS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD977 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converter
AD9772 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 150 MSPS TxDAC⑩ with 2x Interpolation Filter
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*