- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362116 > AD976AR (ANALOG DEVICES INC) 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters PDF資料下載
參數(shù)資料
| 型號： | AD976AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 577K |
| 代理商： | AD976AR |
AD9761
–14–
REV. B
ensure proper compatibility of most TTL logic families. Figure
31 shows the equivalent digital input circuit for the data, sleep
and clock inputs.
RESET
DATA
SELECT
CLOCK/WRITE
I
0
Q
0
I
1
Q
1
Figure 30. Timing Diagram
DVDD
DIGITAL
INPUT
Figure 31. Equivalent Digital Input
Since the AD9761 is capable of being updated up to 40 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the minimum
setup and hold-times of the AD9761 as well as its required
min/max input logic level thresholds. The external clock driver
circuitry should provide the AD9761 with a low jitter clock
input meeting the min/max logic levels while providing fast
edges. Fast clock edges will help minimize any jitter that can
manifest itself as phase noise on a reconstructed waveform.
Digital signal paths should be kept short, and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20
to 100
) between the
AD9761 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs,
which contributes to data feedthrough. Operating the AD9761
with reduced logic swings and a corresponding digital supply
(DVDD) will also reduce data feedthrough.
RESET/SLEEP MODE OPERATION
The RESET/SLEEP input can be used either to power-down
the AD9761 or reset its internal digital interface logic. If the
RESET/SLEEP input is asserted for greater than one clock
cycle but under four clock cycles by applying a Logic Level “1,”
the internal state machine will be reset. If the RESET/SLEEP
input is asserted for four clock cycles or longer, the power-down
function of the AD9761 will be initiated. The power-down
function turns off the output current and reduces the supply
current to less than 9 mA over the specified supply range of 3 V
to 5.5 V and temperature range.
The power-up and power-down characteristics of the AD9761 is
dependent upon the value of the compensation capacitor con-
nected to COMP1 and COMP3. With a nominal value of 0.1
μ
F,
the AD9761 takes less than 5
μ
s to power down and approxi-
mately 3.25 ms to power back up.
POWER DISSIPATION
The power dissipation of the AD9761 is dependent on several
factors which include: (1) AVDD and DVDD, the power supply
voltages; (2) I
OUTFS
, the full-scale current output; (3) f
CLOCK
, the
update rate; (4) and the reconstructed digital input waveform.
The power dissipation is directly proportional to the analog
supply current, I
AVDD
, and the digital supply current, I
DVDD
.
I
AVDD
is directly proportional to I
OUTFS
as shown in Figure 32
and is insensitive to f
CLOCK
.
I
OUTFS
–
mA
30
01
10
2
3
4
5
6
7
8
9
25
20
15
10
5
I
A
–
Figure 32. I
AVDD
vs. I
OUTFS
Conversely, I
DVDD
is dependent on both the digital input wave-
form, f
CLOCK
, and digital supply DVDD. Figures 33 and 34 show
I
DVDD
as a function of a full-scale sine wave output ratio’s (f
OUT
/
f
CLOCK
) for various update rate with DVDD = 5 V and DVDD =
3 V respectively
.
5 MSPS
RATIO
–
f
OUT
/f
CLK
40
30
0.05
0.15
40 MSPS
20
0
0.1
20 MSPS
10 MSPS
10
0
I
D
–
0.2
50
60
70
2.5 MSPS
Figure 33. I
DVDD
vs. Ratio @ DVDD = 5 V
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD976ARS | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters |
| AD976BN | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters |
| AD976BR | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters |
| AD976BRS | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters |
| AD976CN | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD976ARRL | 功能描述:IC ADC 16BIT 100KSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD976ARS | 功能描述:IC ADC 16BIT 100KSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD976ARSRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel 28-Pin SSOP T/R |
| AD976ARSZ | 功能描述:IC ADC 16BIT 100KSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD976ARSZRL | 功能描述:IC ADC 16BIT 100KSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。