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參數(shù)資料
| 型號(hào)： | AD976ACN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converters |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 |
| 封裝： | 0.300 INCH, SKINNY, PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 6/23頁(yè) |
| 文件大?。?/td> | 577K |
| 代理商： | AD976ACN |
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AD9761
–6–
REV. B
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
2–9
10
11
DB9
DB8–DB1
DB0
CLOCK
Most Significant Data Bit (MSB).
Data Bits 1–8.
Least Significant Data Bit (LSB).
Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters read respective
input registers.
Write input. DAC input registers latched on positive edge of write.
Select Input. Select high routes input data to I DAC, select low routes data to Q DAC.
Digital Supply Voltage (2.7 V to 5.5 V).
Digital Common.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
μ
F capacitor.
Q DAC Current Output. Full-scale current when all data bits are 1s.
Q DAC Complementary Current Output. Full-scale current when all data bits are 0s.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V
reference output when internal reference activated. Requires 0.1
μ
F capacitor to ACOM when inter-
nal reference activated.
Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.
Bandwidth/Noise Reduction Node. Add 0.1
μ
F to AVDD for optimum performance.
Analog Supply Voltage (3 V to 5.5 V).
Analog Common.
I DAC Complementary Current Output. Full-scale current when all data bits are 0s.
I DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1
μ
F capacitor.
Power-Down control input if asserted for four clock cycles or longer. Reset control input if asserted
for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/SLEEP
section.
12
13
14
15
16
17
18
19
WRITE
SELECT
DVDD
DCOM
COMP3
QOUTA
QOUTB
REFLO
20
REFIO
21
22
23
24
25
26
27
28
FSADJ
COMP2
AVDD
ACOM
IOUTB
IOUTA
COMP1
RESET/SLEEP
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9761
(MSB) DB9
IOUTB
IOUTA
COMP1
RESET/SLEEP
DB8
DB7
DB6
COMP2
AVDD
ACOM
DB5
DB4
DB3
DB2
DB1
(LSB) DB0
REFLO
REFIO
FSADJ
CLOCK
WRITE
SELECT
DVDD
QOUTB
DCOM
COMP3
QOUTA
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