
REV. A
–2–
AD9768–SPECIFICATIONS
(typical @ +25
8
C under followng conditions unless otherwse noted; nomnal digital
input levels; nomnal power supplies; R
L
= 50
V
; R
SET
= 220
V
; V
RET
= 0 V)
AD9768SD D/A Schematic
Parameter
RESOLUT ION(FS = FULL SCALE)
LSB WEIGHT (CURRENT )
ACCURACY
1
Differential Nonlinearity
Integral Nonlinearity
Monotonicity
Zero Offset (lnitial)
T EMPERAT URE COEFFICIENT S
Zero Offset
Reference Voltage (–1.26 V)
DIGIT AL DAT A INPUT S
Logic Compatibility
Logic Voltage Levels “l(fā)” =
“0” =
Coding
Unit
Bits
μ
A
AD9768SJD/SD/SE
8
78
±
% FS
±
% FS
0.2
0.2
Guaranteed
60
μ
A
ppm/
°
C
ppm/
°
C
1.5
70
ECL
–0.9
–1.7
V
V
Binary (BIN) = Unipolar Out
Offset Binary (OBN) = Bipolar Out
OUT PUT
Current (Unipolar) FS
I
OUT
(@ Pin 13)
All Digital “0” Input
I
OUT
(@ Pin 14)
All Digital “0” Input
Compliance
mA (max)
2 to 20 (30)
mA
mA
20
0
mA
mA
V (Pin 13)
V (Pin 14)
(
±
15%)
0
20
–0.7 to +3.0
–1.1 to +3.0
750
Impedance
SPEED PERFORMANCE
Settling T ime (to 0.2% FS)
2
Slew Rate
Update Rate
Rise T ime
Glitch Energy
REFERENCE
Internal, Monolithic
3
External, Variable
4
Voltage-Multiplying Mode
Current-Multiplying Mode
VOLT AGE-MULT IPLY ING MODE
4
(See Figure 2)
V
M
Range (at Pin 16)
V
Center
Resistance (at Pin 16)
T ransfer Function –
ns
V/
μ
s
MSPS
ns
pV-sec
5
400
100
1.8
200
V
–1.26
V (max)
mA (max)
0 to –1.1 (–2)
0 to –5 (–7.5 )
V
V
k
Measured at Pin 13; Digital “0” Applied
to Bits 1-8:
–0.1 V
M
Input = 0 mA I
OUT
–1.1 V
Input = 0 mA I
Measured at Pin 13; Digital “1” Applied
to Bits 1-8:
–0.1 V
M
Input = 1 mA I
OUT
–1.1 V
M
Input = 20 mA I
OUT
kHz
±
0.5
–0.6
800
Large Signal Bandwidth (–3 dB Point)
250
Parameter
CURRENT -MULT IPLY ING MODE
(See Figure 4)
I
M
Range (at Pins 17 & 18)
Resistance (at Pin 18)
T ransfer Function –
Unit
AD9768SJD/SD/SE
mA
Measured at Pin 13; Digital “0” Applied
to Bits 1-8:
1 mA I
M
Input = 0 mA I
OUT
5 mA I
Input = 0 mA I
Measured at Pin 13; Digital “1” Applied
to Bits 1-8:
1 mA I
M
Input = 4 mA I
OUT
5 mA I
M
Input = 20 mA I
OUT
MHz
0 to 5
160
Large Signal Bandwidth (–3dB Point)
POWER REQUIREMENT S
–5.2 V
±
0.25
+5.0 V
±
0.25
Power Dissipation
Power Supply Sensitivity
5
T EMPERAT URE RANGES
6
Operating
AD9768JD
AD9768SD/SE
Storage
T HERMAL RESlST ANCE
7
Junction to Air,
θ
JA
(Free Air)
Junction to Case,
θ
JA
PACK AGE OPT ION
8
Ceramic (D-18)
40
mA (max)
mA (max)
mW (max)
%/%
66(70)
14(15)
410(430)
0.07
°
C
°
C
°
C
0 to +70
–55 to +125
–55 to +150
°
C/W
°
C/W
90
20
AD9768JD
AD9768SD
AD9768SE
LCC (E-20A)
NOT ES
1
Relative to FS, including linearity (within voltage compliance limits).
2
Worst case settling time; includes FS and Most Significant Bit (MSB) transitions.
3
Applies when operating AD9768 as standard D/A.
4
Based on R
= 50 ohms; R
= 220 ohms; V
= 0 V.
5
1% change in either power supply voltage causes 0.07% change in analog output.
6
Case temperature.
7
Maximum junction temperature 125
°
C.
8
D = Ceramic DIP, E = Leadless Ceramic Chip Carrier.
Specifications subject to change without notice.