參數(shù)資料
型號(hào)： AD9767-EB
廠商： Analog Devices, Inc.
英文描述： 14-Bit, 125 MSPS Dual TxDAC+ D/A Converter
中文描述： 14位，125 MSPS的TxDAC系列雙D / A轉(zhuǎn)換
文件頁(yè)數(shù)： 15/27頁(yè)
文件大?。?/td> 469K
代理商： AD9767-EB
REV. B
AD9767
–15–
I
OUTFS
and R
LOAD
can be selected as long as the positive compli-
ance range is adhered to. One additional consideration in this
mode is the integral nonlinearity (INL) as discussed in the
Analog Output section of this data sheet. For optimum INL
performance, the single-ended, buffered voltage output configu-
ration is suggested.
AD9767
I
OUTA
I
OUTB
50
25
50
V
OUTA
= 0 TO +0.5V
I
OUTFS
= 20mA
Figure 36. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 37 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9767 output current. U1 maintains I
OUTA
(or I
OUTB
) at a
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC’s INL performance as discussed in the
Analog Output section. Although this single-ended configura-
tion typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by U1’s slewing capabilities. U1 provides a negative
unipolar output voltage and its full-scale output voltage is sim-
ply the product of R
FB
and I
OUTFS
. The full-scale output should
be set within U1’s voltage output swing capabilities by scaling
I
OUTFS
and/or R
FB
. An improvement in ac distortion perfor-
mance may result with a reduced I
OUTFS
since the signal current
U1 will be required to sink will be subsequently reduced.
AD9767
I
OUTA
I
OUTB
C
OPT
200
U1
V
OUT
= I
OUTFS
R
FB
I
OUTFS
= 10mA
R
FB
200
Figure 37. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these application cir-
cuits, the implementation and construction of the printed circuit
board is as important as the circuit design. Proper RF tech-
niques must be used for device selection, placement and rout-
ing, as well as power supply bypassing and grounding to ensure
optimum performance. Figures 43 to 50 illustrate the recom-
mended printed circuit board ground, power and signal plane
layouts which are implemented on the AD9767 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the Power Supply Rejection Ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, I
OUTFS
. AC noise on the dc supplies is
common in applications where the power distribution is gener-
ated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR vs. frequency of the AD9767 AVDD
supply over this frequency range is shown in Figure 38.
FREQUENCY
–
MHz
P
–
90
70
0.2
85
80
75
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Figure 38. Power Supply Rejection Ratio of AD9767
Note that the units in Figure 38 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal current sources, and therefore the out-
put current. The voltage noise on AVDD, therefore, will be
added in a nonlinear manner to the desired I
OUT
. PSRR is very
code-dependent thus producing mixing effects which can modu-
late low frequency power supply noise to higher frequencies.
Worst case PSRR for either one of the differential DAC outputs
will occur when the full-scale current is directed towards that
output. As a result, the PSRR measurement in Figure 38 repre-
sents a worst case condition in which the digital inputs remain
static and the full-scale output current of 20 mA is directed to
the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplic-
ity sake (i.e., ignore harmonics), all of this noise is concentrated
at 250 kHz. To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC’s full-scale
current, I
OUTFS
, one must determine the PSRR in dB using
Figure 38 at 250 kHz. To calculate the PSRR for a given R
LOAD
,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 38 by the scaling factor 20
×
Log
(R
LOAD
). For instance, if R
LOAD
is 50
, the PSRR is reduced
by 34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 38, becomes 51 dB V
OUT
/V
IN
).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9767-EBZ 功能描述:BOARD EVAL FOR AD9767 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
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AD9768JD 制造商:Rochester Electronics LLC 功能描述:AD9768 IC - Bulk
AD9768JQ 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD9768SD 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrahigh Speed IC D/A Converter
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