參數(shù)資料
型號(hào)： AD97651
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 125 MSPS Dual TxDAC+ D/A Converter
中文描述： 12位，125 MSPS的TxDAC系列雙D / A轉(zhuǎn)換
文件頁(yè)數(shù)： 12/28頁(yè)
文件大?。?/td> 472K
代理商： AD97651
REV. B
AD9765
–12–
INTERLEAVED MODE TIMING
For the following section, refer to Figure 25.
When the mode pin is at Logic 0, the AD9765 operates in inter-
leaved mode. WRT1 now functions as IQWRT and CLK1
functions as IQCLK. WRT2 functions as IQSEL and CLK2
functions as IQRESET.
Data enters the device on the rising edge of IQWRT. The logic
level of IQSEL will steer the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper
operation, IQSEL should only change state when IQWRT and
IQCLK are low.
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK will update both
DAC latches with the data present at their inputs. In the inter-
leaved mode IQCLK is divided by 2 internally. Following this
first rising edge, the DAC latches will only be updated on every
other rising edge of IQCLK. In this way, IQRESET can be used
to synchronize the routing of the data to the DACs.
As with the dual port mode, IQCLK should occur before or
simultaneously with IQWRT.
IQSEL
IQWRT
DAC1
LATCH
DAC1
INTERLEAVED
DATA IN, PORT 1
DEINTERLEAVED
DATA OUT
IQCLK
IQRESET
DAC2
LATCH
DAC2
2
PORT 1
INPUT
LATCH
PORT 2
INPUT
LATCH
Figure 25. Latch Structure Interleaved Mode
Timing specifications for interleaved mode are given in Figures
26 and 27.
The digital inputs are CMOS-compatible with logic thresholds,
V
THRESHOLD
, set to approximately half the digital positive supply
(DVDD) or
t
S
t
H
t
H*
t
LPW
t
PD
DATA IN
IQSEL
IQWRT
IQCLK
IOUTA
OR
IOUTB
* APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY
Figure 26. Interleaved Mode Timing
INTERLEAVED
DATA
IQSEL
IQWRT
IQCLK
IQRESET
DAC OUTPUT
PORT 1
DAC OUTPUT
PORT 2
XX
D1
D2
D3
D4
D5
XX
XX
D1
D2
D3
D4
Figure 27. Interleaved Mode Timing
The internal digital circuitry of the AD9765 is capable of
operating over a digital supply range of 3 V to 5.5 V. As a
result, the digital inputs can also accommodate TTL levels
when DVDD is set to accommodate the maximum high level
voltage of the TTL drivers V
OH
(MAX). A DVDD of 3 V to
3.3 V will typically ensure proper compatibility with most
TTL logic families. Figure 28 shows the equivalent digital
input circuit for the data and clock inputs. The sleep mode
input is similar with the exception that it contains an active
pull-down circuit, thus ensuring that the AD9765 remains
enabled if this input is left disconnected.
Since the AD9765 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9765
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9765 as well as its required min/max input logic level
thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low
value resistor network (i.e., 20
to 100
) between the AD9765
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
digital feedthrough. For longer board traces and high data up-
date rates, stripline techniques with proper impedance and
termination resistors should be considered to maintain “clean”
digital inputs.
The external clock driver circuitry should provide the AD9765
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
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