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參數(shù)資料
| 型號： | AD9763-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| 中文描述： | 10位，125 MSPS的TxDAC系列雙D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 460K |
| 代理商： | AD9763-EB |
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REV. B
AD9763
–
10
–
GAINCTRL MODE
The AD9763 allows the gain of each channel to be independently
set by connecting one R
SET
resistor to FSADJ1 and another
R
SET
resistor to FSADJ2. To add flexibility and reduce system
cost, a single R
SET
resistor can be used to set the gain of both
channels simultaneously.
When GAINCTRL is low (i.e., connected to AGND), the inde-
pendent channel gain control mode using two resistors is enabled.
In this mode, individual R
SET
resistors should be connected to
FSADJ1 and FSADJ2. When GAINCTRL is high (i.e., connected
to AVDD), the master/slave channel gain control mode using
one resistor is enabled. In this mode, a single R
SET
resistor is
connected to FSADJ1 and the resistor on FSADJ2 must be
removed.
NOTE: Only parts with date code of 9930 or later have the
Master/Slave GAINCTRL function. For parts with a date code
before 9930, Pin 42 must be connected to AGND, and the part
will operate in the two resistor, independent gain control mode.
REFERENCE CONTROL AMPLIFIER
Both of the DACs in the AD9763 contain a control amplifier
that is used to regulate the full-scale output current, I
OUTFS
.
The control amplifier is configured as a V-I converter as shown
in Figure 21, so that its current output, I
REF
, is determined by
the ratio of the V
REFIO
and an external resistor, R
SET
, as stated
in Equation 4. I
REF
is copied to the segmented current sources
with the proper scale factor to set I
OUTFS
as stated in Equa-
tion 3.
The control amplifier allows a wide (10:1) adjustment span of
I
OUTFS
from 2 mA to 20 mA by setting I
REF
between 62.5
μ
A
and 625
μ
A. The wide adjustment range of I
OUTFS
provides
several benefits. The first relates directly to the power dissi-
pation of the AD9763, which is proportional to I
OUTFS
(refer to
the Power Dissipation section). The second relates to the 20dB
adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency,
small signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9763 provide complementary current
outputs, I
OUTA
and I
OUTB
. I
OUTA
will provide a near full-scale
current output, I
OUTFS
, when all bits are high (i.e., DAC CODE
= 1023) while I
OUTB
, the complementary output, provides no
current. The current output appearing at I
OUTA
and I
OUTB
is
a function of both the input code and I
OUTFS
and can be
expressed as:
I
OUTA
= (
DAC CODE
/1024)
×
I
OUTFS
I
OUTB
= (1023 –
DAC CODE
)/1024)
×
I
OUTFS
where
DAC CODE
= 0 to 1023 (i.e., Decimal Representation).
As previously mentioned, I
OUTFS
is a function of the reference
current I
REF
, which is nominally set by a reference voltage,
V
REFIO
and external resistor R
SET
. It can be expressed as:
I
OUTFS
= 32
×
I
REF
where
I
REF
=
V
REFIO
/
R
SET
(1)
(2)
(3)
(4)
The two current outputs will typically drive a resistive load di-
rectly or via a transformer. If dc coupling is required, I
OUTA
and
I
OUTB
should be directly connected to matching resistive loads,
R
LOAD
, that are tied to analog common, ACOM. Note, R
LOAD
may represent the equivalent load resistance seen by I
OUTA
or
I
OUTB
as would be the case in a doubly terminated 50
or
75
cable. The single-ended voltage output appearing at the
I
OUTA
and I
OUTB
nodes is simply:
V
OUTA
=
I
OUTA
×
R
LOAD
V
OUTB
=
I
OUTB
×
R
LOAD
Note the full-scale value of V
OUTA
and V
OUTB
should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
V
DIFF
= (
I
OUTA
– I
OUTB
)
×
R
LOAD
Substituting the values of I
OUTA
, I
OUTB
and I
REF
; V
DIFF
can be
expressed as:
V
DIFF
= {(2
×
DAC CODE
– 1023)/1024}
×
(32
×
R
LOAD
/
R
SET
)
×
V
REFIO
These last two equations highlight some of the advantages of
operating the AD9763 differentially. First, the differential opera-
tion will help cancel common-mode error sources associated
with I
OUTA
and I
OUTB
such as noise, distortion and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, V
DIFF
, is twice the value of the single-ended voltage
output (i.e., V
OUTA
or V
OUTB
), thus providing twice the signal
power to the load.
Note, the gain drift temperature performance for a single-ended
(V
OUTA
and V
OUTB
) or differential output (V
DIFF
) of the AD9763
can be enhanced by selecting temperature tracking resistors for
R
LOAD
and R
SET
due to their ratiometric relationship as shown in
Equation 8.
(5)
(6)
(7)
(8)
ANALOG OUTPUTS
The complementary current outputs in each DAC, I
OUTA
and
I
OUTB
, may be configured for single-ended or differential opera-
tion. I
OUTA
and I
OUTB
can be converted into complementary
single-ended voltage outputs, V
OUTA
and V
OUTB
, via a load resis-
tor, R
LOAD
, as described in the DAC Transfer Function section
by Equations 5 through 8. The differential voltage, V
DIFF
, exist-
ing between V
OUTA
and V
OUTB
can also be converted to a
single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9763 is optimum
and specified using a differential transformer coupled output in
which the voltage swing at I
OUTA
and I
OUTB
is limited to
±
0.5 V.
If a single-ended unipolar output is desirable, I
OUTA
should be
selected.
The distortion and noise performance of the AD9763 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both I
OUTA
and I
OUTB
can be
significantly reduced by the common-mode rejection of a trans-
former or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi-
cant as the frequency content of the reconstructed waveform
increases. This is due to the first order cancellation of various
dynamic common-mode distortion mechanisms, digital feed-
through and noise.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9763-EBZ | 功能描述:BOARD EVAL FOR AD9763 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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| AD9764ARRL | 功能描述:IC DAC 14BIT 125MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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