參數資料
| 型號： | AD9761ARS |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL 40MSPS 28-SSOP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 47 |
| 設置時間： | 35ns |
| 位數： | 10 |
| 數據接口： | 并聯 |
| 轉換器數目： | 2 |
| 電壓電源： | 模擬和數字 |
| 功率耗散（最大）： | 250mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸出數目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 40M |
| 配用： | AD9761-EBZ-ND - BOARD EVAL FOR AD9761 |
AD9761
–14–
AD9761
–15–
result, the digital inputs can also accommodate TTL levels
when DVDD is set to accommodate the maximum high
level voltage, VOH(MAX), of the TTL drivers. A DVDD of 3 V
to 3.3 V will typically ensure proper compatibility of most
TTL logic families. Figure 13 shows the equivalent digital
input circuit for the data, sleep, and clock inputs.
RESET
DATA
SELECT
CLOCK/WRITE
I0
Q0
I1
Q1
Figure 12.Timing Diagram
DVDD
DIGITAL
INPUT
Figure 13. Equivalent Digital Input
Since the AD9761 is capable of being updated up to 40 MSPS,
the quality of the clock and data input signals are important
in achieving the optimum performance. The drivers of the
digital data interface circuitry should be specified to meet
the minimum setup and hold times of the AD9761 as well
as its required min/max input logic level thresholds. The
external clock driver circuitry should provide the AD9761
with a low jitter clock input meeting the min/max logic
levels while providing fast edges. Fast clock edges will help
minimize any jitter that can manifest itself as phase noise
on a reconstructed waveform.
Digital signal paths should be kept short, and run lengths
matched to avoid propagation delay mismatch. The inser-
tion of a low value resistor network (i.e., 20 to 100 )
between the AD9761 digital inputs and driver outputs
may be helpful in reducing any overshooting and ringing at
the digital inputs, which contributes to data feedthrough.
Operating the AD9761 with reduced logic swings and a
corresponding digital supply (DVDD) will also reduce data
feedthrough.
RESET/SLEEP MODE OPERATION
The RESET/SLEEP input can be used either to power down
the AD9761 or reset its internal digital interface logic. If the
RESET/SLEEP input is asserted for greater than one clock
cycle but under four clock cycles by applying a Logic 1, the
internal state machine will be reset. If the RESET/SLEEP input
is asserted for four clock cycles or longer, the power-down func-
tion of the AD9761 will be initiated. The power-down function
turns off the output current and reduces the supply current to
less than 9 mA over the specified supply range of 3 V to 5.5 V
and temperature range.
The power-up and power-down characteristics of the AD9761
are dependent upon the value of the compensation
capacitor connected to COMP1 and COMP3. With a
nominal value of 0.1 F, the AD9761 takes less than 5 s to
power down and approximately 3.25 ms to power back up.
POWER DISSIPATION
The power dissipation of the AD9761 is dependent on several
factors, including
1. AVDD and DVDD, the power supply voltages.
2. IOUTFS, the full-scale current output.
3. fCLOCK, the update rate.
4. The reconstructed digital input waveform.
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD.
IAVDD is directly proportional to IOUTFS, as shown in Fig-
ure 14, and is insensitive to fCLOCK.
IOUTFS (mA)
30
0
1
10
2
3
4
5
6
7
8
9
25
20
15
10
5
I AVDD
(m
A
)
Figure 14. IAVDD vs. IOUTFS
Conversely, IDVDD is dependent on both the digital input
waveform, fCLOCK, and digital supply, DVDD. Figures 15
and 16 show IDVDD as a function of a full-scale sine wave
output ratio’s (fOUT/fCLOCK) for various update rates with
DVDD = 5 V and DVDD = 3 V, respectively.
5MSPS
RATIO (fOUT/fCLK)
40
30
0.05
0.15
40MSPS
20
0
0.10
20MSPS
10MSPS
10
0
I DVDD
(mA
)
0.20
50
60
70
2.5MSPS
Figure 15. IDVDD vs. Ratio @ DVDD = 5 V
REV. C
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