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參數(shù)資料
| 型號： | AD9753ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 300MSPS 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | TxDAC+® |
| 設(shè)置時(shí)間： | 11ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 165mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 300M |
| 配用： | AD9753-EB-ND - BOARD EVAL FOR AD9753 |
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REV. B
–10–
AD9753
IOUTA
IOUTB
SEGMENTED
SWITCHES FOR
DB0 TO DB11
DAC
FSADJ
REFIO
1.2V REF
DIV0
PLLLOCK
DIGITAL DATA INPUTS
0.1 F
RSET
2k
RLOAD
50
DB0 – DB11
DCOM
PMOS CURRENT
SOURCE ARRAY
AVDD
3.0V TO 3.6V
DVDD
2–1 MUX
PORT 1 LATCH
DAC LATCH
ACOM
PORT 2 LATCH
DIV1
PLL
CIRCUITRY
PLLVDD
CLKVDD
CLK+
CLK–
CLKCOM
RESET
LPF
DB0 – DB11
VOUTB
RLOAD
50
VOUTA
VDIFF = VOUTA – VOUTB
Figure 3. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9753. The
AD9753 consists of a PMOS current source array capable of
providing up to 20 mA of full-scale current, IOUTFS. The
array is divided into 31 equal sources that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSBs are a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 k
).
All of the current sources are switched to one of the two
outputs (i.e., IOUTA or IOUTB) via PMOS differential current
switches. The switches are based on a new architecture that
drastically improves distortion performance. This new switch
architecture reduces various timing errors and provides matching
complementary drive signals to the inputs of the differential
current switches.
The analog and digital sections of the AD9753 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.0 V to 3.6 V range. The digital section,
which is capable of operating at a 300 MSPS clock rate, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V band gap voltage refer-
ence, and a reference control amplifier.
The full-scale output current is regulated by the reference control
amplifier and can be set from 2 mA to 20 mA via an external
resistor, RSET. The external resistor, in combination with both
the reference control amplifier and voltage reference VREFIO, sets
the reference current IREF, which is replicated to the segmented
current sources with the proper scaling factor. The full-scale
current, IOUTFS, is 32 times the value of IREF.
REFERENCE OPERATION
The AD9753 contains an internal 1.20 V band gap reference.
This can easily be overdriven by an external reference with no
effect on performance. REFIO serves as either an input or output,
depending on whether the internal or an external reference is
used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1
F capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is to
be used elsewhere in the circuit, an external buffer amplifier
with an input bias current less than 100 nA should be used. An
example of the use of the internal reference is given in Figure 4.
A low impedance external reference can be applied to REFIO,
as shown in Figure 5. The external reference may provide either
a fixed reference voltage to enhance accuracy and drift perfor-
mance or a varying reference voltage for gain control. Note
that the 0.1
F compensation capacitor is not required since
the internal reference is overdriven, and the relatively high input
impedance of REFIO minimizes any loading of the external
reference.
1.2V REF
AVDD
IREF
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
0.1 F
AD9753
REFERENCE
SECTION
ADDITIONAL
EXTERNAL
LOAD
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
Figure 4. Internal Reference Configuration
1.2V REF
AVDD
IREF
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
AD9753
REFERENCE
SECTION
EXTERNAL
REFERENCE
AVDD
Figure 5. External Reference Configuration
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9753-EB | 功能描述:BOARD EVAL FOR AD9753 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9754 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9754AR | 功能描述:IC DAC 14BIT 125MSPS HP 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9754ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH 14-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:14-BIT, 125 MSPS+ TXDAC D/A CONVERTER - Tape and Reel |
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