參數(shù)資料
型號(hào)： AD9750ARUZRL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/22頁(yè)
文件大?。?/td> 0K
描述： IC DAC 10BIT 125MSPS 28TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
系列： TxDAC®
設(shè)置時(shí)間： 35ns
位數(shù)： 10
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 230mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 125M
配用： AD9750-EB-ND - BOARD EVAL FOR AD9750
AD9750
–12–
REV. 0
DIGITAL INPUTS
The AD9750’s digital input consists of 10 data input pins and a
clock input pin. The 10-bit parallel data inputs follow standard
positive binary coding where DB9 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulse-
width. The setup and hold times can also be varied within the
clock cycle as long as the specified minimum times are met;
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling edge
of a 50% duty cycle clock.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD set to approximately half the digital positive supply
(DVDD) or
VTHRESHOLD = DVDD/2 (± 20%)
The internal digital circuitry of the AD9750 is capable of operating
over a digital supply range of 2.7 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure
proper compatibility with most TTL logic families. Figure 23
shows the equivalent digital input circuit for the data and clock
inputs. The sleep mode input is similar with the exception that
it contains an active pull-down circuit, thus ensuring that the
AD9750 remains enabled if this input is left disconnected.
DVDD
DIGITAL
INPUT
Figure 23. Equivalent Digital Input
Since the AD9750 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the minimum
setup and hold times of the AD9750 as well as its required min/
max input logic level thresholds. Typically, the selection of
the slowest logic family that satisfies the above conditions will
result in the lowest data feedthrough and noise.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20
to 100 ) between the
AD9750 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough. For longer run lengths and high
data update rates, strip line techniques with proper termination
resistors should be considered to maintain “clean” digital in-
puts. Also, operating the AD9750 with reduced logic swings and
a corresponding digital supply (DVDD) will also reduce data
feedthrough.
The external clock driver circuitry should provide the AD9750
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
Note, the clock input could also be driven via a sine wave, which is
centered around the digital threshold (i.e., DVDD/2), and meets
the min/max logic threshold. This will typically result in a slight
degradation in the phase noise, which becomes more noticeable
at higher sampling rates and output frequencies. Also, at higher
sampling rates, the 20% tolerance of the digital logic threshold
should be considered since it will affect the effective clock duty
cycle and subsequently cut into the required data setup and
hold times.
INPUT CLOCK/DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9750 is positive edge triggered, and
so exhibits SNR sensitivity when the data transition is close to
this edge. In general, the goal when applying the AD9750 is to
make the data transitions shortly after the rising edge. This
becomes more important as the sample rate increases. Figure 24
shows the relationship of SNR to clock placement with different
sample rates and different frequencies out. Note that at the
lower sample rates, much more tolerance is allowed in clock
placement, while at higher rates, much more care must be taken.
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE – ns
40
–10
15
–5
0
5
10
60
56
52
48
SNR
–
dB
44
FS = 65MSPS
FS = 125MSPS
Figure 24. SNR vs. Clock Placement 2 fOUT = 10 MHz
SLEEP MODE OPERATION
The AD9750 has a power-down function which turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level “1” to the SLEEP pin. This digital input also con-
tains an active pull-down circuit that ensures the AD9750 re-
mains enabled if this input is left disconnected. The AD9750
takes less than 50 ns to power down and approximately 5
s to
power back up.
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