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參數(shù)資料
| 型號(hào)： | AD9737ABBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 11BIT 2.5GSPS RF 160BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 13ns |
| 位數(shù)： | 11 |
| 數(shù)據(jù)接口： | LVDS，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 960µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 160-CSPBGA（12x12） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | 2.5G |
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AD9737A/AD9739A
Data Sheet
Rev. | Page 48 of 64
THEORY OF OPERATION
The AD9739A and the AD9737A are 14- and 11-bit TxDACs
with a specified update rate of 1.6 GSPS to 2.5 GSPS. Figure 157
shows a top-level functional diagram of the AD9737A/AD9739A.
A high performance TxDAC core delivers a signal dependent,
differential current (nominal ±10 mA) to a balanced load
referenced to ground. The frequency of the clock signal appearing
at the AD9737A/AD9739A differential clock receiver, DACCLK,
sets the TxDAC’s update rate. This clock signal, which serves as
the master clock, is routed directly to the TxDAC as well as to a
clock distribution block that generates all critical internal and
external clocks.
The AD9737A/AD9739A include two LVDS data ports (DB0
and DB1) to reduce the data interface rate to the TxDAC
update rate. The host processor drives deinterleaved data with
offset binary format onto the DB0 and DB1 ports, along with
an embedded DCI clock that is synchronous with the data.
Because the interface is double data rate (DDR), the DCI clock
is essentially an alternating 0-1 bit pattern with a frequency that
is equal to the TxDAC update rate (fDAC). To simplify synch-
passes an LVDS clock output (DCO) that is also equal to the
DCI frequency.
The AD9737A/AD9739A data receiver controller generates an
internal sampling clock for the DDR receiver such that the data
instance sampling is optimized. When enabled and configured
properly for track mode, it ensures proper data recovery between
the host and the AD9737A/AD9739A clock domains. The data
receiver controller has the ability to track several hundreds of
picoseconds of drift between these clock domains, typically caused
by supply and temperature variation.
As mentioned, the host processor provides the AD9737A/
AD9739A with a deinterleaved data stream such that the DB0
and DB1 data ports receive alternating samples (that is, odd/even
to reassemble (that is, multiplex) the odd/even data streams
into their original order before delivery into the TxDAC for
signal reconstruction. The pipeline delay from a sample being
latched into the data port to when it appears at the DAC output
is on the order of 78 (±) DACCLK cycles.
The AD9737A/AD9739A includes a delay lock loop (DLL)
circuit controlled via a Mu controller to optimize the timing
hand-off between the AD9737A/AD9739A digital clock domain
and TxDAC core. Besides ensuring proper data reconstruction,
the TxDAC’s ac performance is also dependent on this critical
hand-off between these clock domains with speeds of up to
2.5 GSPS. Once properly initialized and configured for track
mode, the DLL maintains optimum timing alignment over
temperature, time, and power supply variation.
A SPI interface is used to configure the various functional blocks
as well as monitor their status for debug purposes. Proper
operation of the AD9737A/AD9739A requires that controller
blocks be initialized upon power-up. A simple SPI initialization
routine is used to configure the controller blocks (see Table 28).
An IRQ output signal is available to alert the host should any of
the controllers fall out of lock during normal operation.
The following sections discuss the various functional blocks
in more detail as well as their implications when interfacing
to external ICs and circuitry. Although a detailed description of
the various controllers (and associated SPI registers used to
configure and monitor) is also included for completeness, the
recommended SPI boot procedure can be used to ensure
reliable operation.
L
V
DS
DDR
R
EC
EI
VER
DCI
SDO
SDIO
SCLK
CS
DACCLK
DCO
DB0[
13:
0]
DB1[
13:
0]
CLK DISTRIBUTION
(DIV-BY-4)
DAT
A
C
ON
TR
OLLE
R
4
-T
O
-1
DAT
A
AS
S
E
M
BL
E
R
SPI
RESET
DLL
(MU CONTROLLER)
L
V
DS
DDR
R
EC
EI
VER
DAT
A
L
AT
CH
IOUTN
IOUTP
VREF
I120
IRQ
1.2V
DAC BIAS
AD9737A/AD9739A
TxDAC
CORE
09616-
077
C
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9737ABBCZRL | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 11-Bit 2.5 GSPS RF RoHS:否 制造商:Analog Devices 轉(zhuǎn)換器數(shù)量:4 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率: 分辨率:12 bit 接口類型:Serial (I2C) 穩(wěn)定時(shí)間: 最大工作溫度:+ 105 C 安裝風(fēng)格: 封裝 / 箱體:TSSOP 封裝:Reel |
| AD9737A-EBZ | 功能描述:BOARD EVAL FOR AD9737A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9739 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter |
| AD9739A | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter |
| AD9739ABBC | 制造商:Analog Devices 功能描述:14 BIT 2.5 GSPS DAC A REVISION - Trays |
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