參數(shù)資料
型號(hào)： AD9736BBCRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/72頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 1.2GSPS 160CSPBGA
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 550mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 160-CSPBGA（12x12）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 1.2G
AD9734/AD9735/AD9736
Rev. A | Page 35 of 72
THEORY OF OPERATION
The AD9736, AD9735, and AD9734 are 14-bit, 12-bit, and
10-bit DACs that run at an update rate up to 1.2 GSPS. Input
data can be accepted up to the full 1.2 GSPS rate, or a 2×
interpolation filter can be enabled (2× mode) allowing full
speed operation with a 600 MSPS input data rate. The DATA
and DATACLK_IN inputs are parallel LVDS, meeting the IEEE
reduced swing LVDS specifications with the exception of input
hysteresis. The DATACLK_IN input runs at one-half the input
DATA rate in a double data rate (DDR) format. Each edge of
DATACLK_IN transfers DATA into the AD9736, as shown in
The DACCLK/DACCLK+ inputs (Pin E1 and Pin F1) directly
drive the DAC core to minimize clock jitter. The DACCLK
signal is also divided by 2 (1× and 2× mode), then output as the
DATACLK_OUT. The DATACLK_OUT signal clocks the data
source. The DAC expects DDR LVDS data (DB<13:0>) aligned
with the DDR input clock (DATACLK_IN) from a circuit simi-
lar to the one shown in Figure 96. Table 19 shows the clock
relationships.
Table 19. AD973x Clock Relationship
MODE
DACCLK
DATACLK_OUT
DATACLK_IN
DATA
1×
1.2 GHz
600 MHz
1.2 GSPS
2×
1.2 GHz
600 MHz
300 MHz
600 MSPS
Maintaining correct alignment of data and clock is a common
challenge with high speed DACs, complicated by changes in
temperature and other operating conditions. Using the
DATACLK_OUT signal to generate the data allows most of the
internal process, temperature, and voltage delay variation to be
cancelled. The AD973x further simplifies this high speed data
capture problem with two adaptive closed-loop timing
controllers.
One timing controller manages the LVDS data and data clock
alignment (LVDS controller), and the other manages the LVDS
data and DACCLK alignment (sync controller).
The LVDS controller locates the data transitions and delays the
DATACLK_IN so that its transition is in the center of the valid
data window. The sync controller manages the FIFO that moves
data from the LVDS DATACLK_IN domain to the DACCLK
domain.
Both controllers can operate in manual mode under external
processor control, in surveillance mode where error conditions
generate external interrupts, or in automatic mode where errors
are automatically corrected.
The LVDS and sync controllers include moving average filtering
for noise immunity and variable thresholds to control activity.
Normally, the controllers are set to run in automatic mode,
making any necessary adjustments without dropping or dupli-
cating samples sent to the DAC. Both controllers require initial
calibration prior to entering automatic update mode.
The AD973x analog output changes 35 DACCLK cycles after
the input data changes in 1× mode with the FIFO disabled. The
FIFO adds up to eight additional cycles of delay. This delay is
read from the SPI port. Internal clock delay variation is less
than a single DACCLK cycle at 1.2 GHz (833 ps).
Stopping the AD973x DATACLK_IN while the DACCLK is still
running can lead to unpredictable output signals. This occurs
because the internal digital signal path is interleaved. The last
two samples clocked into the DAC continue to be clocked out
by DACCLK even after DATACLK_IN has stopped. The result-
ing output signal is at a frequency of one-half fDAC, and the
amplitude depends on the difference between the last two
samples.
Control of the AD973x functions is via the serially programmed
registers listed in Table 9. Optionally, a limited number of func-
tions can be directly set by external pins in pin mode.
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參數(shù)描述
AD9736BBCZ 功能描述:IC DAC 14BIT 1.2GSPS 160CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD9736BBCZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS
AD9736BBCZRL 功能描述:IC DAC 14BIT 1.2GSPS 160CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:*
AD9736BBCZRL1 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS
AD9736-DPG2-EBZ 功能描述:BOARD EVAL FOR AD9736 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
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