參數(shù)資料
型號: AD9734BBCZRL
廠商: Analog Devices Inc
文件頁數(shù): 46/72頁
文件大?。?/td> 0K
描述: IC DAC 10BIT 1.2GSPS 160-CSPBGA
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 550mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 160-CSPBGA(12x12)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 1.2G
AD9734/AD9735/AD9736
Rev. A | Page 50 of 72
APPLICATIONS INFORMATION
DRIVING THE DACCLK INPUT
The DACCLK input requires a low jitter differential drive
signal. It is a PMOS input differential pair powered from the
1.8 V supply, so it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 800 mV p-p about the 400 mV common-
mode voltage. While these input levels are not directly LVDS
compatible, DACCLK can be driven by an offset ac-coupled
LVDS signal, as shown in Figure 90.
04862-088
LVDS_P_IN
CLK+
50
Ω
50
Ω
0.1
μF
0.1
μF
LVDS_N_IN
CLK–
VCM = 400mV
Figure 90. LVDS DACCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to DACCLK, as shown in Figure 107. Use of a CMOS or TTL
clock can also be acceptable for lower sample rates. It is routed
through a CMOS to LVDS translator, then ac-coupled, as
described previously. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 91.
04862-089
50
Ω
50
Ω
TTL OR CMOS
CLK INPUT
CLK+
CLK–
VCM = 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
0.1
μF
Figure 91. TTL or CMOS DACCLK Drive Circuit
A simple bias network for generating VCM is shown in
Figure 92. It is important to use CVDD18 and CVSS for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and may
degrade the DAC performance.
0
48
62-
0
90
0.1F
1nF
VCM = 400mV
CVDD
1.8V
CVSS
1k
287
Figure 92. DACCLK VCM Generator Circuit
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