參數(shù)資料
型號: AD9717BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 39/80頁
文件大?。?/td> 0K
描述: IC DAC DUAL 14BIT LO PWR 40LFCSP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC®
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 86mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 托盤
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 125M
產(chǎn)品目錄頁面: 785 (CN2011-ZH PDF)
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 44 of 80
DAC TRANSFER FUNCTION
The AD9714/AD9715/AD9716/AD9717 provide two differen-
tial current outputs, IOUTP/IOUTN and QOUTP/QOUTN.
IOUTP and QOUTP provide a near full-scale current output,
IxOUTFS, when all bits are high (that is, DAC CODE = 2N 1,
where N = 8, 10, 12, or 14 for the AD9714, AD9715, AD9716,
and AD9717, respectively), while IOUTN and QOUTN, the
complementary outputs, provide no current. The current
outputs appearing at the positive DAC outputs, IOUTP and
QOUTP, and at the negative DAC outputs, IOUTN and QOUTN,
are a function of both the input code and IxOUTFS and can be
expressed as follows:
IOUTP = (IDAC CODE/2N) × IIOUTFS
(1)
QOUTP = (QDAC CODE/2N) × IQOUTFS
IOUTN = ((2N 1) IDAC CODE)/2N × IIOUTFS
(2)
QOUTN = ((2N 1) QDAC CODE)/2N × IQOUTFS
where:
IDAC CODE and QDAC CODE = 0 to 2N 1 (that is, decimal
representation).
IIOUTFS and IQOUTFS are functions of the reference currents, IIREF
and IQREF, respectively, which are nominally set by a reference
voltage, VREFIO, and external resistors, IRSET and QRSET, respec-
tively. IIOUTFS and IQOUTFS can be expressed as follows:
IIOUTFS = 32 × IIREF
(3)
IQOUTFS = 32 × IQREF
where:
IIREF = VREFIO/IRSET
(4)
IQREF = VREFIO/QRSET
or
IIOUTFS = 32 × VREFIO/IRSET
(5)
IQOUTFS = 32 × VREFIO/QRSET
A differential pair (IOUTP/IOUTN or QOUTP/QOUTN)
typically drives a resistive load directly or via a transformer. If
dc coupling is required, the differential pair (IOUTP/IOUTN or
QOUTP/QOUTN) should be connected to matching resistive
loads, xRLOAD, that are tied to analog common, AVSS. The
single-ended voltage output appearing at the positive and
negative nodes is
VIOUTP = IOUTP × IRLOAD
(6)
VQOUTP = QOUTP × QRLOAD
VIOUTN = IOUTN × IRLOAD
(7)
VQOUTN = QOUTN × QRLOAD
To achieve the maximum output compliance of 1 V at the
nominal 4 mA output current, IRLOAD = QRLOAD must be set
to 250 Ω.
Substituting the values of IOUTP, IOUTN, and IxREF, VIDIFF can
be expressed as
VIDIFF = {(2 × IDAC CODE – (2N 1))/2N} ×
(8)
(32 × VREFIO/IRSET) × IRLOAD
Equation 8 highlights some of the advantages of operating the
AD9714/AD9715/AD9716/AD9717 differentially. First, the
differential operation helps cancel common-mode error sources
associated with IOUTP and IOUTN, such as noise, distortion,
and dc offsets. Second, the differential code-dependent current and
subsequent voltage, VIDIFF, is twice the value of the single-ended
voltage output (that is, VIOUTP or VIOUTN), thus providing twice
the signal power to the load. Note that the gain drift temperature
performance for a single-ended output (VIOUTP and VIOUTN) or
differential output (VIDIFF) of the AD9714/AD9715/AD9716/
AD9717 can be enhanced by selecting temperature-tracking
resistors for xRLOAD and xRSET because of their ratiometric
relationship, as shown in Equation 8.
ANALOG OUTPUT
The complementary current outputs in each DAC, IOUTP/
IOUTN and QOUTP/QOUTN, can be configured for single-
ended or differential operation. IOUTP/IOUTN and QOUTP/
QOUTN can be converted into complementary single-ended
voltage outputs, VIOUTP and VIOUTN, as well as VQOUTP and VQOUTN
via a load resistor, xRLOAD, as described in the DAC Transfer
Function section by Equation 6 through Equation 8. The differen-
tial voltages, VIDIFF and VQDIFF, existing between VIOUTP and VIOUTN,
and VQOUTP and VQOUTN, can also be converted to a single-ended
voltage via a transformer or a differential amplifier configuration.
The ac performance of the AD9714/AD9715/AD9716/AD9717
is optimum and is specified using a differential transformer-
coupled output in which the voltage swing at IOUTP and IOUTN
is limited to ±0.5 V. The distortion and noise performance of
the AD9714/AD9715/AD9716/AD9717 can be enhanced when
it is configured for differential operation. The common-mode
error sources of both IOUTP/IOUTN and QOUTP/QOUTN
can be significantly reduced by the common-mode rejection
of a transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed wave-
form increases and/or its amplitude increases. This is due to
the first-order cancellation of various dynamic common-mode
distortion mechanisms, digital feedthrough, and noise. Performing
a differential-to-single-ended conversion via a transformer also
provides the ability to deliver twice the reconstructed signal
power to the load (assuming no source termination). Because
the output currents of IOUTP/IOUTN and QOUTP/QOUTN
are complementary, they become additive when processed
differentially.
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