參數(shù)資料
型號： AD9707-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 44/44頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9707
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD9704/AD9705/AD9706/AD9707
Rev. B | Page 9 of 44
AD9707
AD9706
AD9705
AD9704
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
Power Supply Rejection
Ratio (AVDD)6
2
0.1
+2
2
0.1
+2
2
0.1
+2
2
0.1
+2
% of
FSR/V
OPERATING RANGE
40
+85
40
+85
40
+85
40
+85
°C
1 Measured at IOUTA, driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32 × the IREF current.
3 Use an external buffer amplifier with an input bias current <100 nA to drive any external load.
4 Measured at IOUTFS = 1 mA.
5 Measured at fCLOCK = 80 MSPS and fOUT = 1 MHz, using a differential clock.
6 ±5% power supply variation.
DYNAMIC SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 1 mA, differential transformer coupled output, 453 Ω differentially
terminated unless otherwise noted.
Table 5.
AD9707
AD9706
AD9705
AD9704
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate, fCLOCK
125
MSPS
Output Settling Time, tST, (to 0.1%)1
11
ns
Output Propagation Delay (tPD)
5.6
ns
Glitch Impulse
5
pV-s
Output Rise Time (10% to 90%)1
2.5
ns
Output Fall Time (10% to 90%)1
2.5
ns
AC LINEARITY
Spurious-Free Dynamic Range to
Nyquist
fCLOCK = 10 MSPS; fOUT = 2.1 MHz
86
85
70
dBc
fCLOCK = 25 MSPS; fOUT = 2.1 MHz
87
86
84
68
dBc
fCLOCK = 25 MSPS; fOUT = 5.1 MHz
82
68
dBc
fCLOCK = 65 MSPS; fOUT = 10.1 MHz
82
79
78
70
dBc
fCLOCK = 65 MSPS; fOUT = 15.1 MHz
77
76
74
69
dBc
fCLOCK = 80 MSPS; fOUT = 1.0 MHz
74
82
72
82
72
82
66
70
dBc
fCLOCK = 80 MSPS; fOUT = 15.1 MHz
77
68
dBc
fCLOCK = 80 MSPS; fOUT = 30.1 MHz
60
59
60
dBc
Noise Spectral Density
fCLOCK = 80 MSPS; fOUT = 10 MHz;
IOUTFS = 1 mA
145
144
140
128
dBc/Hz
fCLOCK = 80 MSPS; fOUT = 10 MHz;
IOUTFS = 2 mA
151
dBc/Hz
1 Measured single-ended into 500 Ω load.
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