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參數(shù)資料
| 型號(hào)： | AD96685BRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP SNGL ULTRA-FAST 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補(bǔ)充型，ECL，開路發(fā)射極 |
| 電壓 - 輸入偏移（最小值）： | 2mV @ -5.2V，5V |
| 電流 - 輸入偏壓（最小值）： | 10µA @ -5.2V，5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 18mA，36mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 90dB CMRR，70dB PSRR |
| 傳輸延遲（最大）： | 3.5ns |
| 工作溫度： | -25°C ~ 85°C |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
REV. D
–2–
AD96685/AD96687–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (Positive Supply Voltage = 5.0 V; Negative Supply Voltage = –5.2 V, unless otherwise noted.)
Industrial Temperature Range –25 C to +85 C
Test
AD96685BR
AD96687BQ/BP/BR
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Offset Voltage
25
°CI
1
2
1
2
mV
Full
VI
3
mV
Input Offset Drift
Full
V
20
V/°C
Input Bias Current
25
°CI
7
10
7
10
A
Full
VI
13
A
Input Offset Current
25
°C
I
0.1
1.0
0.1
1.0
A
Full
VI
1.2
A
Input Resistance
25
°C
V
200
k
Input Capacitance
25
°CV
2
pF
Input Voltage Ranges
2
Full
VI
–2.5
+5.0
–2.5
+5.0
V
Common-Mode Rejection Ratio
Full
VI
80
90
80
90
dB
ENABLE INPUT
Logic “1” Voltage
Full
VI
–1.1
V
Logic “0” Voltage
Full
VI
–1.5
V
Logic “1” Current
Full
VI
40
A
Logic “0” Current
Full
VI
5
A
DIGITAL OUTPUTS
3
Logic “1” Voltage
Full
VI
–1.1
V
Logic “0” Voltage
Full
VI
–1.5
V
SWITCHING PERFORMANCES
Propagation Delays
4
Input to Output HIGH
25
°C
IV
2.5
3.5
2.5
3.5
ns
Input to Output LOW
25
°C
IV
2.5
3.5
2.5
3.5
ns
Latch Enable to Output HIGH
25
°C
IV
2.5
3.5
2.5
3.5
ns
Latch Enable to Output LOW
25
°C
IV
2.5
3.5
2.5
3.5
ns
Dispersions
5
25
°C
V
50
ps
Latch Enable
Minimum Pulsewidth
25
°C
IV
2.0
3.0
2.0
3.0
ns
Minimum Setup Time
25
°C
IV
0.5
1.0
0.5
1.0
ns
Minimum Hold Time
25
°C
IV
0.5
1.0
0.5
1.0
ns
POWER SUPPLY
6
Positive Supply Current (+5.0 V)
Full
VI
8
9
15
18
mA
Negative Supply Current (–5.2 V)
Full
VI
15
18
31
36
mA
Power Supply Rejection Ratio
7
Full
VI
60
70
60
70
dB
NOTES
1R
S = 100
.
2Input Voltage Range can be extended to –3.3 V if –V
S = –6.0 V.
3Outputs terminated through 50
to –2.0 V.
4Propagation delays measured with 100 mV pulse (10 mV overdrive) to 50% transition point of the output.
5Change in propagation delay from 100 mV to 1 V input overdrive.
6Supply voltages should remain stable within
± 5% for normal operation.
7Measured at
±5% of +V
S and –VS.
Specifications subject to change without notice.
COMPARE
LATCH
ENABLE
DIFFERENTIAL
INPUT
VOLTAGE
50%
VOS
50%
tS
VIN
VDD
tH
tPW(E)
tPD(E)
tPD
Q
tS
tH
tPD
tPD(E)
tPW(E)
VOS
VOD
– Minimum Setup Time
– Minimum Hold Time
– Input to Output Delay
– LATCH ENABLE to Output Delay
– Minimum LATCH ENABLE Pulsewidth
– Input Offset Voltage
– Overdrive Voltage
Figure 1. System Timing Diagram
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