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參數(shù)資料
型號(hào)： AD9637BCPZRL7-40
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/40頁(yè)
文件大小： 0K
描述： IC ADC 12BIT SRL 40MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 40M
數(shù)據(jù)接口： LVDS，串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 414mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： *
輸入數(shù)目和類型： 8 個(gè)差分
AD9637
Data Sheet
Rev. A | Page 26 of 40
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 1 or 511 bits. A description
of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value
is all 1s (see Table 12 for the initial values). The output is a parallel
representation of the serial PN9 sequence in MSB first format.
The first output word is the first 12 bits of the PN9 sequence in
MSB aligned format.
Table 12. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First) Twos Complement
PN Sequence Short
0x1FE0
0x1DF1, 0x3CC8, 0x294E
PN Sequence Long
0x1FFF
0x1FE0, 0x2001, 0x1C00
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
seed value is all 1s (see Table 12 for the initial values) and the
AD9637 inverts the bit stream with relation to the ITU standard.
The output is a parallel representation of the serial PN23 sequence
in MSB first format. The first output word is the first 12 bits of the
PN23 sequence in MSB aligned format.
See the Memory Map section for information on how to change
these additional digital output timing features through the SPI.
SDIO/DFS Pin
For applications that do not require SPI mode operation, the
CSB pin is tied to AVDD, and the SDIO/DFS pin controls the
output data format select operation according to Table 13.
Table 13. Output Data Format Select Pin Settings
DFS Pin Voltage
Output Mode
AVDD
Twos complement
GND (Default)
Offset binary
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test
pattern if it and the CSB pin are both held high during device
power-up. When SCLK/DTP is tied to AVDD, the ADC channel
outputs shift out the following pattern: 1000 0000 0000. The
FCO and DCO function normally while all channels shift out the
repeatable test pattern. This pattern allows the user to perform
timing alignment adjustments among the FCO, DCO, and output
data. This pin has an internal 30 k resistor to GND. It can be
left unconnected for normal operation.
Table 14. Digital Test Pattern Pin Settings
Selected DTP
DTP Voltage
Resulting D± x
Normal Operation
No connect
Normal operation
DTP
AVDD
1000 0000 0000
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map section
for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. Tying CSB high causes all
SCLK and SDIO information to be ignored.
RBIAS Pin
To set the internal core bias current of the ADC, place
a 10.0 k, 1% tolerance resistor to ground at the RBIAS pin.
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