- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10055 > AD9633BCPZRL7-80 (Analog Devices Inc)IC ADC 12BIT SRL 80MSPS 48LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9633BCPZRL7-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL 80MSPS 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | LVDS，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 389mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-WQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)差分，雙極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Data Sheet
AD9633
Rev. 0 | Page 33 of 40
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into three sections: the chip
configuration registers (Address 0x00 to Address 0x02); the device
index and transfer registers (Address 0x05 and Address 0xFF);
and the global ADC functions registers, including setup, control,
and test (Address 0x08 to Address 0x109).
The memory map register table (see Table 17) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x05, the device
index register, has a hexadecimal default value of 0x3F. This
means that in Address 0x05, Bits[7:6] = 0, and the remaining
Bits[5:0] = 1. This setting is the default channel index setting.
The default value results in both ADC channels receiving the
next write command. For more information on this function
and others, see the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI. This application note details the functions
controlled by Register 0x00 to Register 0xFF. The remaining
registers are documented in the Memory Map Register
Descriptions section.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x05). If the entire address location
is open or not listed in Table 17 (for example, Address 0x13), this
address location should not be written.
Default Values
After the AD9633 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel. In
these cases, channel address locations are internally duplicated
for each channel. These registers and bits are designated in
Table 17 as local. These local registers and bits can be accessed
by setting the appropriate data channel bits (A, B, C, or D) and
the clock channel DCO bit (Bit 5) and FCO bit (Bit 4) in
Register 0x05. If all the bits are set, the subsequent write affects
the registers of all channels and the DCO/FCO clock channels.
In a read cycle, only one of the channels (A, B, C, or D) should
be set to read one of the four registers. If all the bits are set
during a SPI read cycle, the part returns the value for Channel
A. Registers and bits designated as global in Table 17 affect the
entire part or the channel features for which independent
settings are not allowed between channels. The settings in
Register 0x05 do not affect the global registers and bits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-264-MX-F3 | CONVERTER MOD DC/DC 48V 75W |
| MS27468T19F32P | CONN RCPT 32POS JAM NUT W/PINS |
| AD674BKN | IC ADC 12BIT MONO 3OUT 28-DIP |
| IDT72225LB10J | IC FIFO 1024X18 SYNC 10NS 68PLCC |
| AD7876CR | IC ADC 12BIT SAMPLING 10V 24SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9634 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170 MSPS/210 MSPS/250 MSPS |
| AD9634-170EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 12 Bit 170 Msps ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9634-210EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 12 Bit 210 Msps ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9634-250EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 12 Bit 250 Msps ADC RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9634BCPZ-170 | 功能描述:IC ADC 12BIT 170MSPS 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。