參數(shù)資料
型號(hào)： AD9629BCPZ-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 65MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 86mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，單極；1 個(gè)差分，單極
AD9629
Rev. 0 | Page 17 of 32
THEORY OF OPERATION
The AD9629 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors in
the preceding stage. The quantized outputs from each stage are
combined into a final 12-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with a
new input sample while the remaining stages operate with pre-
ceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the CMOS output buffers. The output buffers
are powered from a separate (DRVDD) supply, allowing adjust-
ment of the output voltage swing. During power-down, the output
buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9629 is a differential switched-
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
SS
H
CPAR
CSAMPLE
CPAR
VIN–
H
SS
H
VIN+
H
08
54
0-
0
06
Figure 34. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample-and-hold mode (see Figure 34). When the input circuit
is switched to sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current injected from the output
stage of the driving source. In addition, low Q inductors or ferrite
beads can be placed on each leg of the input to reduce high dif-
ferential capacitance at the analog inputs and, therefore, achieve
the maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end at
high IF frequencies. Either a shunt capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter at the
input to limit unwanted broadband noise. See the AN-742
Application Note, the AN-827 Application Note, and the Analog
A/D Converters” (Volume 39, April 2005) for more information.
In general, the precise values depend on the application.
Input Common Mode
The analog inputs of the AD9629 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide a
dc bias externally. Setting the device so that VCM = AVDD/2
is recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 35 and Figure 36.
An on-board, common-mode voltage reference is included in
the design and is available from the VCM pin. The VCM pin
must be decoupled to ground by a 0.1 μF capacitor, as described
100
90
80
70
60
50
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
INPUT COMMON-MODE VOLTAGE (V)
S
N
R
/SF
D
R
(
d
B
F
S/
d
B
c
)
08
54
0-
1
49
SFDR (dBc)
SNR (dBFS)
Figure 35. SNR/SFDR vs. Input Common-Mode Voltage,
fIN = 32.1 MHz, fS = 80 MSPS
100
90
80
70
60
50
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
INPUT COMMON-MODE VOLTAGE (V)
S
N
R/
S
F
DR
(
d
B
F
S
/d
B
c
)
08
54
0-
1
50
SFDR (dBc)
SNR (dBFS)
Figure 36. SNR/SFDR vs. Input Common-Mode Voltage,
fIN = 10.3 MHz, fS = 20 MSPS
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