參數(shù)資料
型號： AD9613BCPZRL7-170
廠商： Analog Devices Inc
文件頁數(shù)： 16/36頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 170MSPS 64LFCSP
標準包裝： 750
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 738mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個差分，雙極
Data Sheet
AD9613
Rev. C | Page 23 of 36
THEORY OF OPERATION
The AD9613 has two analog input channels, two filter channels,
and two digital output channels. The intermediate frequency (IF)
input signal passes through several stages before appearing at the
output port(s) as a filtered, and optionally, decimated digital signal.
The dual ADC design can be used for diversity reception of signals,
where the ADCs operate identically on the same carrier but from
two separate antennae. The ADCs can also be operated with
independent analog inputs. The user can sample frequencies
from dc to 300 MHz using appropriate low-pass or band-pass
filtering at the ADC inputs with little loss in ADC performance.
Operation to 400 MHz analog input is permitted but occurs at
the expense of increased ADC noise and distortion.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9613 are accomplished
using a 3-pin, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9613 architecture consists of a dual front-end sample-
and-hold circuit, followed by a pipelined, switched-capacitor
ADC. The quantized outputs from each stage are combined into
a final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-ended
modes. The output staging block aligns the data, corrects errors,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing digital output noise to be
separated from the analog core. During power-down, the output
buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9613 is a differential switched-capacitor
circuit that has been designed for optimum performance while
processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 46).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within 1/2 clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, the
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to the AN-742 Application Note, Frequency
Domain Response of Switched-Capacitor ADCs; the AN-827
Application Note, A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs; and the Analog Dialogue article,
for more information on this subject.
CPAR1
CPAR2
S
CFB
CS
BIAS
VIN+
09637-
050
H
VIN–
Figure 46. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
VIN+ and VIN should be matched, and the inputs should be
differentially balanced.
Input Common Mode
The analog inputs of the AD9613 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board
common-mode voltage reference is included in the design and
is available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM
pin must be decoupled to ground by a 0.1 F capacitor, as described
in the Applications Information section. Place this decoupling
capacitor close to the pin to minimize the series resistance and
inductance between the part and this capacitor.
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