參數(shù)資料
型號： AD9608BCPZRL7-125
廠商： Analog Devices Inc
文件頁數(shù)： 21/40頁
文件大小： 0K
描述： IC ADC 10BIT 125MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 10
采樣率（每秒）： 125M
數(shù)據(jù)接口： LVDS，并聯(lián)，串行，SPI
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，2 個差分
AD9608
Rev. 0 | Page 28 of 40
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
]
)
10
/
(
LF
SNR
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 59.
80
75
70
65
60
55
50
45
1
10
100
1k
FREQUENCY (MHz)
S
N
R
(dB
FS
)
0.5ps
0.2ps
0.05ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
099
77-
065
Figure 59. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9608.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
For more information, see the AN-501 Application Note and the
AN-756 Application Note, available on www.analog.com.
CHANNEL/CHIP SYNCHRONIZATION
The AD9608 has a SYNC input that offers the user flexible
synchronization options for synchronizing sample clocks
across multiple ADCs. The input clock divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence. The SYNC input is internally synchronized
to the sample clock; however, to ensure that there is no timing
uncertainty between multiple parts, the SYNC input signal should
be externally synchronized to the input clock signal, meeting the
setup and hold times shown in Table 5. Drive the SYNC input
using a single-ended CMOS-type signal.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 60, the analog core power dissipated by
the AD9608 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs are determined
primarily by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (22, in the case of the
AD9608).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 60 was
taken in CMOS mode using the same operating conditions as those
used for the power supplies and power consumption parameters
in Table 1, with a 5 pF load on each output driver.
40
90
140
190
240
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
5
2545
6585
105
125
PO
W
ER
(m
W
)
S
UP
P
LY
CURRE
NT
(
mA)
ENCODE RATE (Msps)
IAVDD
IDRVDD
TOTAL POWER
0
9977-
03
0
Figure 60. AD9608-125 Power and Current vs. Clock Rate
(1.8 V CMOS Output Mode)
40
90
140
190
240
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
5
152535455565758595
105
P
OWE
R
(
m
W)
S
UP
P
LY
CU
RRE
N
T
(m
A)
ENCODE RATE (Msps)
IAVDD
IDRVDD
TOTAL POWER
0997
7-
0
23
Figure 61. AD9608-105 Power and Current vs. Clock Rate
(1.8 V CMOS Output Mode)
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