參數(shù)資料
型號(hào)： AD9522-2BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 40/84頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.2GHZ VCO 64LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.33GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
AD9522-2
Rev. 0 | Page 45 of 84
Duty-cycle correction requires the following channel divider
conditions:
An even division must be set as M = N.
An odd division must be set as M = N + 1.
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2) expressed as a percent.
The duty cycle at the output of the channel divider for various
configurations is shown in Table 34 to Table 37.
Table 34. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is 50%
VCO
Divider
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div
DCC = 0
Even
Channel
divider
bypassed
50%
Odd = 3
Channel
divider
bypassed
33.3%
50%
Odd = 5
Channel
divider
bypassed
40%
50%
Even, odd
Even
(N + 1)/(N + M + 2)
50%, requires
M = N
Even, odd
Odd
(N + 1)/(N + M + 2)
50%, requires
M = N + 1
Table 35. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is X%
VCO
Divider
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div DCC = 0
Even
Channel
divider
bypassed
50%
Odd = 3
Channel
divider
bypassed
33.3%
(1 + X%)/3
Odd = 5
Channel
divider
bypassed
40%
(2 + X%)/5
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Even
Odd
(N + 1)/
(N + M + 2)
50%, requires M = N + 1
Odd = 3
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Odd = 3
Odd
(N + 1)/
(N + M + 2)
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
Odd = 5
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Odd = 5
Odd
(N + 1)/
(N + M + 2)
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Table 36. Channel Divider Output Duty Cycle When the
VCO Divider Is Enabled and Set to 1
Input
Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div DCC = 0
Any
Even
(N + 1)/
(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/
(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/
(M + N + 2)
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
Note that the channel divider must be enabled when the VCO
divider = 1.
Table 37. Channel Divider Output Duty Cycle When the
VCO Divider Is Bypassed
Input
Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div DCC = 0
Any
Channel
divider
bypassed
Same as input
duty cycle
Same as input duty
cycle
Any
Even
(N + 1)/
(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/
(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/
(M + N + 2)
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO divider equals 1, the duty cycle is 50%. If the CLK input is
routed directly to the output, the duty cycle of the output is the
same as the CLK input.
Phase Offset or Coarse Time Delay
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 38).
These settings determine the number of cycles (successive rising
edges) of the channel divider input frequency by which to offset, or
delay, the rising edge of the output of the divider. This delay is
with respect to a nondelayed output (that is, with a phase offset
of zero). The amount of the delay is set by five bits loaded into
the phase offset (PO) register plus the start high (SH) bit for
each channel divider. When the start high bit is set, the delay is
also affected by the number of low cycles (M) programmed for
the divider.
It is necessary to use the SYNC function to make phase offsets
section).
Table 38. Setting Phase Offset and Division
Divider
Start
High (SH)
Phase
Offset (PO)
Low Cycles
M
High Cycles
N
0
0x191[4]
0x191[3:0]
0x190[7:4]
0x190[3:0]
1
0x194[4]
0x194[3:0]
0x193[7:4]
0x193[3:0]
2
0x197[4]
0x197[3:0]
0x196[7:4]
0x196[3:0]
3
0x19A[4]
0x19A[3:0]
0x199[7:4]
0x199[3:0]
相關(guān)PDF資料
PDF描述
AD9522-3BCPZ-REEL7 IC CLOCK GEN 2GHZ VCO 64LFCSP
AD9522-4BCPZ-REEL7 IC CLOCK GEN 1.6GHZ VCO 64LFCSP
AD9522-5BCPZ IC CLOCK GEN 2.4GHZ 64LFCSP
AD9523-1BCPZ-REEL7 IC INTEGER-N CLCK GEN 72LFCSP
AD9523BCPZ IC INTEGER-N CLCK GEN 72LFCSP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9522-2BCPZ-REEL7 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9522-3 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 2 GHz VCO
AD9522-3/PCBZ 功能描述:BOARD EVAL FOR AD9522-3 CLK GEN RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
AD9522-3BCPZ 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
AD9522-3BCPZ-REEL7 功能描述:IC CLOCK GEN 2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*