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參數(shù)資料
| 型號： | AD9522-0BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 73/84頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.95GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9522-0
Rev. 0 | Page 75 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
0F6
[7:0]
OUT6 control
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
0F7
[7:0]
OUT7 control
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
0F8
[7:0]
OUT8 control
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
0F9
[7:0]
OUT9 control
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
0FA
[7:0]
OUT10 control
This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
0FB
[7:0]
OUT11 control
This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
0FC
[7]
CSDLD En OUT7 OUT7 is enabled only if CSDLD is high.
[7]
CSDLD Signal
OUT7 Enable Status
0
Not affected by CSDLD signal (default).
1
0
Asynchronous power-down.
1
Asynchronously enable OUT7 if not powered down by other settings.
To use this feature, the user must use current source digital lock detect,
and set the enable LD pin comparator bit (0x01D[3]).
0FC
[6]
CSDLD En OUT6 OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[5]
CSDLD En OUT5 OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[4]
CSDLD En OUT4 OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[3]
CSDLD En OUT3 OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[2]
CSDLD En OUT2 OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[1]
CSDLD En OUT1 OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC
[0]
CSDLD En OUT0 OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[3]
CSDLD En
OUT11
OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[2]
CSDLD En
OUT10
OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[1]
CSDLD En OUT9 OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FD
[0]
CSDLD En OUT8 OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Table 54. LVDS Channel Dividers
Reg.
Addr
(Hex) Bit(s) Name
Description
190
[7:4]
Divider 0 low cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).
190
[3:0]
Divider 0 high cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7).
191
[7]
Divider 0 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use the divider (default).
[7] = 1; bypass the divider.
191
[6]
Divider 0 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
191
[5]
Divider 0 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
191
[4]
Divider 0 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
191
[3:0]
Divider 0 phase offset
Phase offset (default: 0x0).
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| AD9522-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 2.4 GHz VCO |
| AD9522-1/PCBZ | 功能描述:BOARD EVAL FOR AD9522-1 CLK GEN RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9522-1BCPZ | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9522-1BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9522-2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
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