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參數(shù)資料
| 型號： | AD9520-4BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 配用： | AD9520-4/PCBZ-ND - BOARD EVAL FOR AD9520-4 |
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Data Sheet
AD9520-4
Rev. A | Page 47 of 80
Note that the value stored in the register equals the number of
cycles minus one. For example, Register 0x190[7:4] = 0001b
equals two low cycles (M = 2) for Divider 0.
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX (in
seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0].
The channel divide-by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15,
Δt = Φ × TX
Δc = Δt/TX = Φ
Case 2
For Φ ≥ 16,
Δt = (Φ 16 + M + 1) × TX
Δc = Δt/TX
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Tx
DIVIDER 0
DIVIDER 1
DIVIDER 2
CHANNEL
DIVIDER INPUT
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
1 × Tx
2 × Tx
07217-
071
CHANNEL DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
Figure 51. Effect of Coarse Phase Offset (or Delay)
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 51 shows the results of setting such a coarse
offset between outputs.
Synchronizing the Outputs— SYNC Function
The AD9520 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions. These conditions include the
divider ratio and phase offsets for a given channel divider. This
allows the user to specify different divide ratios and phase offsets
for each of the four channel dividers. Releasing the SYNC pin
allows the outputs to continue clocking with the preset conditions
applied.
Synchronization of the outputs is executed in the following ways:
The SYNC pin is forced low and then released (manual sync).
By setting and then resetting any one of the following three
bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit
(Register 0x000[5] [mirrored]), and the power-down
distribution reference bit (Register 0x230[1]).
Synchronization of the outputs can be executed as part of
the chip power-up sequence.
The RESET pin is forced low and then released (chip reset).
The PD pin is forced low, then released (chip power-down).
When a VCO calibration is completed, an internal SYNC
signal is automatically asserted at the beginning and
released upon the completion of a VCO calibration.
The most common way to execute the SYNC function is to use
the SYNC pin to perform a manual synchronization of the outputs.
This requires a low-going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The timing
of the SYNC operation is shown in Figure 52 (using the VCO
divider) and in Figure 53 (the VCO divider is not used). There
is an uncertainty of up to one cycle of the clock at the input to
the channel divider due to the asynchronous nature of the SYNC
signal with respect to the clock edges inside the AD9520.
The pipeline delay from the SYNC rising edge to the beginning
of the synchronized output clocking is between 14 cycles and
15 cycles of clock at the channel divider input, plus either one
cycle of the VCO divider input (see Figure 52), or one cycle of
the channel divider input (see Figure 53), depending on whether
the VCO divider is used. Cycles are counted from the rising
edge of the signal. In addition, there is an additional 1.2 ns (typical)
delay from the SYNC signal to the internal synchronization logic,
as well as the propagation delay of the output driver. The driver
propagation delay is approximately 100 ps for the LVPECL
driver and approximately 1.5 ns for the CMOS driver.
Another common way to execute the SYNC function is by setting
and resetting the soft SYNC bit at Register 0x230[0]. Both setting
and resetting of the soft SYNC bit require an update all registers
(Register 0x232[0] = 1b) operation to take effect.
A SYNC operation brings all outputs that have not been excluded
(by the ignore SYNC bit) to a preset condition before allowing
the outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static state
of each output when the SYNC operation is happening and the
state and relative phase of the outputs when they begin clocking
again upon completion of the SYNC operation. Between outputs
and after synchronization, this allows for the setting of phase offsets.
The AD9520 differential LVPECL outputs are four groups of
three, sharing a channel divider per triplet. In the case of CMOS,
each LVPECL differential pair can be configured as two single-
ended CMOS outputs. The synchronization conditions apply to
all of the drivers that belong to that channel divider.
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the ignore SYNC bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the included channels.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9520-4BCPZ-REEL7 | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9520-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator |
| AD9520-5/PCBZ | 功能描述:BOARD EVAL FOR AD9520-5 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9520-5BCPZ | 功能描述:IC CLOCK GEN EXT VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9520-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN EXT VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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