參數(shù)資料
    型號(hào)： AD9520-2BCPZ
    廠商： Analog Devices Inc
    文件頁(yè)數(shù)： 46/80頁(yè)
    文件大?。?/td> 0K
    描述： IC CLOCK GEN 2.2GHZ VCO 64LFCSP
    設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
    Phase Coherent FSK Modulator (CN0186)
    標(biāo)準(zhǔn)包裝： 1
    類型： 時(shí)鐘發(fā)生器，扇出配送
    PLL： 是
    輸入： CMOS，LVDS，LVPECL
    輸出： CMOS，LVPECL
    電路數(shù)： 1
    比率 - 輸入:輸出： 2:12，2:24
    差分 - 輸入:輸出： 是/是
    頻率 - 最大： 2.33GHz
    除法器/乘法器： 是/無(wú)
    電源電壓： 3.135 V ~ 3.465 V
    工作溫度： -40°C ~ 85°C
    安裝類型： 表面貼裝
    封裝/外殼： 64-VFQFN 裸露焊盤，CSP
    供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
    包裝： 托盤
    產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
    AD9520-2
    Data Sheet
    Rev. A | Page 50 of 80
    Hardware Reset via the RESET Pin
    RESET, a hard reset (an asynchronous hard reset is executed by
    briefly pulling RESET low), restores the chip either to the setting
    stored in the EEPROM (the EEPROM pin = 1b) or to the on-chip
    setting (the EEPROM pin = 0b). A hard reset also executes
    a SYNC operation, bringing the outputs into phase alignment
    according to the default settings. When the EEPROM is inactive
    (the EEPROM pin = 0b), it takes ~2 s for the outputs to begin
    toggling after RESET is issued. When the EEPROM is active
    (the EEPROM pin = 1b), it takes ~20 ms for the outputs to toggle
    after RESET is brought high.
    Soft Reset via the Serial Port
    The serial port control register allows for a soft reset by setting
    Bit 2 and Bit 5 in Register 0x000. The function of this register is
    determined by the state of the EEPROM pin.
    When Bit 2 and Bit 5 are set and the EEPROM pin is high, the
    chip is restored to the settings saved in the EEPROM. When Bit
    2 and Bit 5 are set and the EEPROM pin is low, the chip is
    restored to the on-chip defaults.
    Except for the self-clearing bits, Bit 2 and Bit 5, Register 0x000
    retains its previous value prior to reset. During the internal reset,
    the outputs hold static. However, the self-clearing operation
    does not complete until an additional serial port SCLK cycle
    occurs, and the AD9520 is held in reset until that happens.
    Soft Reset to Settings in EEPROM when EEPROM Pin = 0b
    via the Serial Port
    If the EEPROM pin is low, the serial port control register allows
    the chip to be reset to settings in EEPROM via Register 0xB02[1].
    (Bit 1 is self-clearing.) This bit does not have any effect when the
    EEPROM pin is high. It takes ~20 ms for the outputs to begin
    toggling after the SOFT_EEPROM register is cleared.
    POWER-DOWN MODES
    Chip Power-Down via PD
    The AD9520 can be put into a power-down condition by pulling
    the PD pin low. Power-down turns off most of the functions and
    currents inside the AD9520. The chip remains in this power-down
    state until PD is brought back to logic high. When taken out
    of power-down mode, the AD9520 returns to the settings
    programmed into its registers prior to the power-down, unless
    the registers are changed by new programming while the PD
    pin is held low.
    Powering down the chip shuts down the currents on the chip,
    except for the bias current necessary to maintain the LVPECL
    outputs in a safe shutdown mode. The LVPECL bias currents are
    needed to protect the LVPECL output circuitry from damage that
    can be caused by certain termination and load configurations
    when tristated. Because this is not a complete power-down, it
    can be called sleep mode. The AD9520 contains special circuitry to
    prevent runt pulses on the outputs when the chip is entering or
    exiting sleep mode.
    When the AD9520 is in a PD power-down, the chip is in the
    following state:
    The PLL is off (asynchronous power-down).
    The VCO is off.
    The CLK input buffer is off, but the CLK input dc bias
    circuit is on.
    In differential mode, the reference input buffer is off, but
    the dc bias circuit is still on.
    In singled-ended mode, the reference input buffer is off,
    and the dc bias circuit is off.
    All dividers are off.
    All CMOS outputs are tristated.
    All LVPECL outputs are in safe off mode.
    The serial control port is active, and the chip responds to
    commands.
    PLL Power-Down
    The PLL section of the AD9520 can be selectively powered
    down. There are two PLL power-down modes set by
    Register 0x010[1:0]: asynchronous and synchronous.
    In asynchronous power-down mode, the device powers down as
    soon as the registers are updated. In synchronous power-down
    mode, the PLL power-down is gated by the charge pump to
    prevent unwanted frequency jumps. The device goes into power-
    down on the occurrence of the next charge pump event after the
    registers are updated.
    Distribution Power-Down
    The distribution section can be powered down by writing
    Register 0x230[1] = 1b, which turns off the bias to the distribution
    section. If the LVPECL power-down mode is in normal operation
    (Register 0x230[1] = 0b), it is possible for a low impedance load
    on that LVPECL output to draw significant current during this
    power-down. If the LVPECL power-down mode is set to 1b, the
    LVPECL output is not protected from reverse bias and can be
    damaged under certain termination conditions.
    Individual Clock Output Power-Down
    Any of the clock distribution outputs can be powered down
    into safe power-down mode by individually writing to the
    appropriate registers. The register map details the individual
    power-down settings for each output. These settings are found
    in Bit 0 of Register 0x0F0 to Register 0x0FB.
    Individual Clock Channel Power-Down
    Any of the clock distribution channels can be powered down
    individually by writing to the appropriate registers. Powering
    down a clock channel is similar to powering down an individual
    driver, but it saves more power because the dividers are also
    powered down. Powering down a clock channel also automatically
    powers down the drivers connected to it. The register map
    details the individual power-down settings for each output
    channel. These settings are found in Bit 2 of Register 0x192,
    Register 0x195, Register 0x198, and Register 0x19B.
    相關(guān)PDF資料
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