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參數(shù)資料
| 型號： | AD9520-1BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/80頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.65GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 配用： | AD9520-1/PCBZ-ND - BOARD EVAL FOR AD9520-1 |
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Data Sheet
AD9520-1
Rev. A | Page 39 of 80
External VCXO/VCO Clock Input (CLK/CLK)
This differential input is used to drive the AD9520 clock
distribution section. This input can receive up to 2.4 GHz.
The pins are internally self-biased, and the input signal should
be ac-coupled via capacitors.
VS
CLOCK INPUT
STAGE
CLK
5k
2.5k
07214-
032
Figure 46. CLK Equivalent Input Circuit
The CLK/CLK input can be used either as a distribution only
input (with the PLL off) or as a feedback input for an external
VCO/VCXO using the internal PLL when the internal VCO is
not used. These inputs are also used as a feedback path for the
external zero delay mode.
Holdover Mode
The AD9520 PLL has a holdover function. Holdover mode allows
the VCO to maintain a relatively constant frequency even though
there is no reference clock. This function is useful when the PLL
reference clock is lost. Holdover is implemented by placing the
charge pump in a high impedance state. Without this function,
the charge pump is placed into a constant pump-up or pump-down
state, resulting in a massive VCO frequency shift. Because the
charge pump is placed in a high impedance state, any leakage
that occurs at the charge pump output or the VCO tuning node
causes a drift of the VCO frequency. This drift can be mitigated
by using a loop filter that contains a large capacitive component
because this drift is limited by the current leakage-induced slew
rate (ILEAK/C) of the VCO control voltage.
Both a manual holdover mode, using the SYNC pin, and an
automatic holdover mode are provided. To use either function, the
holdover function must be enabled (Register 0x01D[0]).
Manual/External Holdover Mode
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves the
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state if no reference
clock is present.
The B counter (in the N divider) is reset synchronously with the
charge pump, leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close, resulting in a smaller phase difference for the loop to
settle out.
When using this mode, set the channel dividers to ignore the
SYNC pin (at least after an initial SYNC event). If the dividers are
not set to ignore the SYNC pin, the distribution outputs turn off
when SYNC is taken low to put the part into holdover mode. The
channel divider ignore SYNC function is programmed in Bit 6 of
Register 0x191, Register 0x194, Register 0x197, and Register 0x19A
for Channel Divider 0, Channel Divider 1, Channel Divider 2, and
Channel Divider 3, respectively.
Automatic/Internal Holdover Mode
When enabled, this function automatically places the charge
pump into a high impedance state when the loop loses lock.
The assumption is that the only reason the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappeared.
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the DLD,
ALD, or current source LD mode. The LD comparator can be
disabled (Register 0x01D[3]), which causes the holdover function
to always sense LD as being high. If DLD is used, it is possible
for the DLD signal to chatter while the PLL is reacquiring lock.
The holdover function may retrigger, thereby preventing the
holdover mode from terminating. Use of the current source lock
detect mode is recommended to avoid this situation (see the
When in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
is reset synchronously with the charge pump leaving the high
impedance state on the reference path PFD event. This helps
align the edges out of the R and N dividers for faster settling of
the PLL and reduces frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and
R numbers are close because this results in a smaller phase
difference for the loop to settle out.
After leaving holdover, the loop then reacquires lock, and the
LD pin must go high (if Register 0x01D[3] = 1b) before it can
reenter holdover (CP high impedance).
The holdover function always responds to the state of the
currently selected reference (Register 0x01C). If the loop loses
lock during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference clock
edge at the PFD.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9520-1BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9520-2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
| AD9520-2/PCBZ | 功能描述:BOARD EVAL AD9520-2 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9520-2BCPZ | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9520-2BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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