參數(shù)資料
型號: AD9518-4ABCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 64/64頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 6CH 1.8GHZ 48LFCSP
標(biāo)準(zhǔn)包裝: 750
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.8GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
Data Sheet
AD9518-4
Rev. B | Page 9 of 64
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL and
VCO; uses rising edge of clock signal
CLK = 622.08 MHz; LVPECL = 622.08 MHz;
Divider = 1
40
fs rms
BW = 12 kHz to 20 MHz
CLK = 622.08 MHz; LVPECL = 155.52 MHz;
Divider = 4
80
fs rms
BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
215
fs rms
Calculated from SNR of ADC method; DCC not used
for even divides
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
245
fs rms
Calculated from SNR of ADC method; DCC on
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
210
fs rms
Calculated from SNR of ADC method
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