參數(shù)資料
型號(hào)： AD9518-3ABCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/64頁(yè)
文件大小： 0K
描述： IC CLOCK GEN 6CH 2GHZ 48LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.25GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤(pán)
AD9518-3
Data Sheet
Rev. B | Page 24 of 64
Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the channel
dividers does not exceed their specified maximum frequency of
1600 MHz (see Table 3). The internal PLL uses an external loop
filter to set the loop bandwidth. The external loop filter is also
crucial to the loop stability.
When using the internal VCO, it is necessary to calibrate the
VCO (Register 0x018[0]) to ensure optimal performance.
For internal VCO and clock distribution applications, use the
register settings that are shown in Table 23.
Table 23. Settings When Using an Internal VCO
Register
Function
0x010[1:0] = 00b
PLL normal operation (PLL on).
0x010 to 0x01D
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP
according to the intended loop configuration.
0x018[0] = 0b,
0x232[0] = 1b
Reset VCO calibration. This process is not
required the first time after power-up, but it
must be performed subsequently.
0x1E0[2:0]
Set VCO divider to divide-by-2, divide-by-3,
divide-by-4, divide-by-5, or divide-by-6.
0x1E1[0] = 0b
Use VCO divider as the source for the
distribution section.
0x1E1[1] = 1b
Select VCO as the source.
0x018[0] = 1b,
0x232[0] = 1b
Initiate VCO calibration.
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
REF1
REF2
STATUS
R
DIVIDER
VCO STATUS
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_ SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
BYPASS
LF
LOW DROPOUT
REGULATOR (LDO)
VCO
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
RE
NCE
HOLD
OUT0
OUT1
OUT0
OUT1
LVPECL
DIVIDE BY
1 TO 32
OUT2
OUT3
OUT2
OUT3
LVPECL
DIVIDE BY
1 TO 32
0
1
DIVIDE BY
2, 3, 4, 5, OR 6
PD
SYNC
RESET
SCLK
SDIO
SDO
CS
DIGITAL
LOGIC
SERIAL
CONTROL
PORT
OUT4
OUT5
OUT4
OUT5
LVPECL
DIVIDE BY
1 TO 32
06
43
2-
03
0
AD9518-3
Figure 29. Internal VCO and Clock Distribution
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9518-3ABCPZ-RL7 功能描述:IC CLOCK GEN 6CH 2GHZ 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9518-3A-PCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with 6-Output Clock Generator with
AD9518-3BCPZ 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9518-3BCPZ-REEL7 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP T/R
AD9518-4 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 1.6 GHz VCO
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