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參數(shù)資料
| 型號： | AD9518-0ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 6CH 2.8GHZ 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.95GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
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AD9518-0
Data Sheet
Rev. C | Page 50 of 64
Reg.
Addr.
(Hex)
Bits
Name
Description
[1:0]
Antibacklash pulse
width
1
0
Antibacklash Pulse Width (ns)
0
2.9 (default); this is the recommended setting, and it does not normally need to be changed.
0
1
1.3; this setting may be necessary if the PFD frequency > 50 MHz.
1
0
6.0.
1
2.9.
0x018
[6:5]
Lock detect counter
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
5
PFD Cycles to Determine Lock
0
5 (default).
0
1
16.
1
0
64.
1
255.
4
Digital lock detect
window
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
3
Disable digital lock
detect
Digital lock detect operation.
0: normal lock detect operation (default).
1: disables lock detect.
[2:1]
VCO cal divider
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
2
1
VCO Calibration Clock Divider
0
2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R.
0
1
4. This setting is fine for PFD frequencies < 25 MHz.
1
0
8. This setting is fine for PFD frequencies < 50 MHz.
1
16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time.
0
VCO cal now
Bit used to initiate VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate calibration,
use the following three steps: first, ensure that the input reference signal is present; second, set to 0b (if not zero
already), followed by the update all registers bit (Register 0x232, Bit 0); and third, program to 1b, again followed by the
update all registers bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the
PLL losing lock. The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration.
0x019
[7:6]
R, A, B counters,
SYNC pin reset
7
6
Action
0
Does nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
Does nothing on SYNC.
[5:3]
R path delay
R path delay (default = 0x00); see Table 2.
[2:0]
N path delay
N path delay (default = 0x00); see Table 2.
相關(guān)PDF資料 |
PDF描述 |
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| AD9518-1ABCPZ | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
| AD9518-2ABCPZ-RL7 | IC CLOCK GEN 6CH 2.2GHZ 48LFCSP |
| AD9518-3ABCPZ | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
| AD9518-4ABCPZ-RL7 | IC CLOCK GEN 6CH 1.8GHZ 48LFCSP |
| AD9520-0BCPZ-REEL7 | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9518-0ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 2.8GHZ 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9518-0A-PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator |
| AD9518-0BCPZ | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray |
| AD9518-0BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9518-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 2.5 GHz VCO |
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