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參數(shù)資料
| 型號： | AD9517-3ABCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.0GHZ VCO 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
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AD9517-3
Data Sheet
Rev. E | Page 48 of 80
12
3
4
5
6
7
8
910
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
1
11
12
13
14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
06
42
7-
0
73
Figure 57. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
INPUT TO CLK
IINPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
12
3
4
5
6
7
8
910
11
12
13
14
1
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
0
64
27
-07
4
Figure 58. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
A sync operation brings all outputs that have not been excluded
(by the nosync bit) to a preset condition before allowing the
outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static
state of each output when the sync operation is happening and
the state and relative phase of the outputs when they begin clocking
again upon completion of the sync operation. Between outputs
and after synchronization, this allows for the setting of phase
offsets.
The AD9517 outputs are in pairs, sharing a channel divider per
pair (two pairs of pairs, four outputs, in the case of CMOS). The
synchronization conditions apply to both outputs of a pair.
Each channel (a divider and its outputs) can be excluded from
any sync operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a sync operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
Clock Outputs
The AD9517 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0 to OUT3 are LVPECL
differential outputs; and OUT4 to OUT7 are LVDS/CMOS
outputs. These outputs can be configured as either LVDS
differential or as pairs of single-ended CMOS outputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9517-4ABCPZ-RL7 | IC CLOCK GEN 1.8GHZ VCO 48LFCSP |
| AD9518-0ABCPZ | IC CLOCK GEN 6CH 2.8GHZ 48LFCSP |
| AD9518-1ABCPZ | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
| AD9518-2ABCPZ-RL7 | IC CLOCK GEN 6CH 2.2GHZ 48LFCSP |
| AD9518-3ABCPZ | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9517-3BCPZ | 制造商:Analog Devices 功能描述: |
| AD9517-3BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9517-3BCPZ-TR | 制造商:Analog Devices 功能描述:12-OUTPUT CLOCK GENERATOR WITH INTEGRATED 2.0 GHZ VCO - Tape and Reel |
| AD9517-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9517-4A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9517-4A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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