- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9158 > AD9517-2ABCPZ (Analog Devices Inc)IC CLOCK GEN 2.2GHZ VCO 48LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9517-2ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 59/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 2.2GHZ VCO 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.33GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當(dāng)前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
AD9517-2
Data Sheet
Rev. E | Page 62 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x017
[1:0]
Antibacklash
1
0
Antibacklash Pulse Width (ns)
pulse width
0
2.9 (default). This is the recommended setting; it does not normally need to be changed.
0
1
1.3. This setting may be necessary if the PFD frequency > 50 MHz.
1
0
6.0.
1
2.9.
0x018
[6:5]
Lock detect
counter
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
5
PFD Cycles to Determine Lock
0
5 (default).
0
1
16.
1
0
64.
1
255.
4
Digital lock detect
window
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
3
Disable digital
Digital lock detect operation.
lock detect
0: normal lock detect operation (default).
1: disables lock detect.
[2:1]
VCO cal divider
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
2
1
VCO Calibration Clock Divider
0
2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R.
0
1
4. This setting is fine for PFD frequencies < 25 MHz.
1
0
8. This setting is fine for PFD frequencies < 50 MHz.
1
16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time.
0
VCO cal now
Bit used to initiate the VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate
calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0b (if
not zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1b, followed by another update
bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the PLL losing lock.
The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration.
0x019
[7:6]
R, A, B counters
7
6
Action
SYNC pin reset
0
Does nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
Does nothing on SYNC.
[5:3]
R path delay
R path delay (default = 0x00) (see Table 2).
[2:0]
N path delay
N path delay (default = 0x00) (see Table 2).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9517-3ABCPZ | IC CLOCK GEN 2.0GHZ VCO 48LFCSP |
| AD9517-1ABCPZ | IC CLOCK GEN 2.5GHZ VCO 48LFCSP |
| V110A48H300BL2 | CONVERTER MOD DC/DC 48V 300W |
| AD9511BCPZ | IC CLOCK DIST 5OUT PLL 48LFCSP |
| V110A48H300BL | CONVERTER MOD DC/DC 48V 300W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9517-2ABCPZ-RL7 | 功能描述:IC CLOCK GEN 2.2GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9517-2BCPZ | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray |
| AD9517-2BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9517-2BCPZ-TR | 制造商:Analog Devices 功能描述:OUPUT CLOCK GENERATOR WITH 2.2HZ VCO - Tape and Reel |
| AD9517-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Output Clock Generator with Integrated 2.0 GHz VCO |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。