參數(shù)資料
型號： AD9516-2BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 37/80頁
文件大?。?/td> 0K
描述： IC CLOCK PLL/VCO 2.2GHZ 64LFCSP
標準包裝： 1
類型： 時鐘發(fā)生器，扇出配送
PLL： 是
輸入： 時鐘
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:14
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.33GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
配用： AD9516-2/PCBZ-ND - BOARD EVAL FOR AD9516-2 2.2GHZ
AD9516-2
Data Sheet
Rev. C | Page 42 of 80
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)
The duty cycle of the clock signal at the output of a channel is
a result of some or all of the following conditions:
What are the M and N values for the channel?
Is the DCC enabled?
Is the VCO divider used?
What is the CLK input duty cycle? (The internal VCO has
a 50% duty cycle.)
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the DCCOFF bit for that channel.
Certain M and N values for a channel divider result in a non-50%
duty cycle. A non-50% duty cycle can also result with an even
division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
An even division must be set as M = N
An odd division must be set as M = N + 1
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2), expressed as a percentage (%).
The duty cycle at the output of the channel divider for various
configurations is shown in Table 35 to Table 37.
Table 35. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%
VCO
Divider
DX
Output Duty Cycle
N + M + 2
DCCOFF = 1
DCCOFF = 0
Even
1 (divider
bypassed)
50%
Odd = 3
1 (divider
bypassed)
33.3%
50%
Odd = 5
1 (divider
bypassed)
40%
50%
Even, Odd
Even
(N + 1)/
(N + M + 2)
50%; requires M = N
Even, Odd
Odd
(N + 1)/
(N + M + 2)
50%; requires M = N + 1
Table 36. Duty Cycle with VCO Divider, Input Duty Cycle Is X%
VCO
Divider
DX
Output Duty Cycle
N + M + 2
DCCOFF = 1
DCCOFF = 0
Even
1 (divider
bypassed)
50%
Odd = 3
1 (divider
bypassed)
33.3%
(1 + X%)/3
Odd = 5
1 (divider
bypassed)
40%
(2 + X%)/5
Even
(N + 1)/
(N + M + 2)
50%,
requires M = N
Odd
(N + 1)/
(N + M + 2)
50%,
requires M = N + 1
Odd = 3
Even
(N + 1)/
(N + M + 2)
50%,
requires M = N
Odd = 3
Odd
(N + 1)/
(N + M + 2)
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
Odd = 5
Even
(N + 1)/
(N + M + 2)
50%,
requires M = N
Odd = 5
Odd
(N + 1)/
(N + M + 2)
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Table 37. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
Input
Clock
Duty
Cycle
DX
Output Duty Cycle
N + M + 2
DCCOFF = 1
DCCOFF = 0
Any
1
1 (divider
bypassed)
Same as input
duty cycle
Any
Even
(N + 1)/
(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/
(M + N + 2)
50%, requires
M = N + 1
X%
Odd
(N + 1)/
(M + N + 2)
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
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