參數(shù)資料
型號(hào): AD9287-100EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 27/52頁(yè)
文件大小: 0K
描述: BOARD EVALUATION AD9287
設(shè)計(jì)資源: AD9219/28/59/87 Gerber Files
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 4
位數(shù): 8
采樣率(每秒): 100M
數(shù)據(jù)接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 530mW @ 100MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9287
已供物品: 板,電源
產(chǎn)品目錄頁(yè)面: 780 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD9287BCPZRL7-100DKR-ND - IC ADC 8BIT QUAD 100MSPS 48LFCSP
AD9287BCPZRL7-100CT-ND - IC ADC 8BIT QUAD 100MSPS 48LFCSP
Data Sheet
AD9287
Rev. E | Page 33 of 52
Addr.
(Hex)
Register Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Default Notes/
Comments
14
output_mode
X
0 = LVDS
ANSI-644
(default)
1 = LVDS
low power
(IEEE
1596.3
similar)
X
Output
invert
1 = on
0 = off
(default)
00 = offset binary
(default)
01 = twos
complement
0x00
Configures the
outputs and the
format of the
data.
15
output_adjust
X
Output driver
termination
00 = none (default)
01 = 200
10 = 100
11 = 100
X
0x00
Determines
LVDS or other
output properties.
Primarily func-
tions to set the
LVDS span and
common-mode
levels in place of
an external
resistor.
16
output_phase
X
0011 = output clock phase adjust
(0000 through 1010)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0101 = 300° relative to data edge
0110 = 360° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03
On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock.
Internal latching
is unaffected.
19
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User-defined
pattern, 1 LSB.
1A
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
0x00
User-defined
pattern, 1 MSB.
1B
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User-defined
pattern, 2 LSB.
1C
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
0x00
User-defined
pattern, 2 MSB.
21
serial_control
LSB first
1 = on
0 = off
(default)
X
<10
MSPS,
low
encode
rate
mode
1 = on
0 = off
(default)
000 = 8 bits (default, normal bit
stream)
001 = 8 bits
010 = 10 bits
011 = 12 bits
100 = 14 bits
0x00
Serial stream
control. Default
causes MSB first
and the native
bit stream
(global).
22
serial_ch_stat
X
Channel
output
reset
1 = on
0 = off
(default)
Channel
power-
down
1 = on
0 = off
(default)
0x00
Used to power
down individual
sections of a
converter (local).
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