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參數(shù)資料
| 型號： | AD9286-500EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9286-500 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 1.2 Vpp |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9286 |
| 已供物品： | 板 |
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8-Bit, 500 MSPS, 1.8 V
Analog-to-Digital Converter (ADC)
Data Sheet
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2011–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Single 1.8 V supply operation
SNR: 49.3 dBFS at 200 MHz input at 500 MSPS
SFDR: 65 dBc at 200 MHz input at 500 MSPS
Low power: 315 mW at 500 MSPS
On-chip interleaved clocking
On-chip reference and track-and-hold
1.2 V p-p analog input range for each channel
Differential input with 500 MHz bandwidth
LVDS-compliant digital output
On-chip voltage reference and sample-and-hold circuit
DNL: ±0.2 LSB
Serial port control options
Interleaved clock timing adjustment
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Built-in selectable digital test pattern generation
Pin-programmable power-down function
Available in 48-lead LFCSP
APPLICATIONS
Battery-powered instruments
Handheld scope meters
Low cost digital oscilloscopes
OTS: video over fiber
GENERAL DESCRIPTION
The AD9286 is an 8-bit, monolithic sampling, analog-to-digital
converter (ADC) that supports interleaved operation and is
optimized for low cost, low power, and ease of use. Each ADC
operates at up to a 250 MSPS conversion rate with outstanding
dynamic performance.
The AD9286 takes a single sample clock and, with an on-chip
clock divider, time interleaves the two ADC cores (each running
at one-half the clock frequency) to achieve the rated 500 MSPS.
By using the SPI, the user can accurately adjust the timing of the
sampling edge per ADC to minimize the image spur energy.
The ADC requires a single 1.8 V supply and an encode clock for
full performance operation. No external reference components
are required for many applications. The digital outputs are LVDS
compatible.
The AD9286 is available in a Pb-free, 48-lead LFCSP that is
specified over the industrial temperature range of 40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Integrated 8-Bit, 500 MSPS ADC.
2. Single 1.8 V Supply Operation with LVDS Outputs.
3. Power-Down Option Controlled via a Pin-Programmable
Setting.
FUNCTIONAL BLOCK DIAGRAM
AD9286
CLK–
VIN1+
VIN1–
VREF
VCM
ADC
CLOCK
MANAGEMENT
CLK+
AUXCLK+
AUXCLK–
VIN2–
VIN2+
×1.5
1.0V
VREF
REF
SELECT
DCO
GENERATION
DCO+
DCO–
RBIAS AUXCLKEN AGND
AVDD
DRVDD
DRGND
SPI
SDIO/
PWDN
OE
SCLK
CSB
D7+ (MSB), D7– (MSB)
D0+ (LSB), D0– (LSB)
L
V
DS
OU
TP
U
T
B
U
FFE
R
O
UT
P
UT
INT
E
RL
E
AV
E
09338-
001
Figure 1.
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