- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10060 > AD9271BSVZRL-25 (Analog Devices Inc)IC ADC OCT 12BIT 25MSPS 100-TQFP PDF資料下載
參數(shù)資料
| 型號： | AD9271BSVZRL-25 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC OCT 12BIT 25MSPS 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 25M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 1.06W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
AD9271
Rev. B | Page 25 of
60
LNA INPUT-REFERRED
NOISE FLOOR
(5.4V rms) @ AAF BW = 15MHz
LNA + VGA NOISE = 1.4nV/ Hz
Crosspoint Switch
Each LNA is followed by a transconductance amp for V/I con-
version. Currents can be routed to one of six pairs of differential
outputs or to 12 single-ended outputs for summing. Each CWD
output pin sinks 2.4 mA dc current, and the signal has a full-scale
current of ±2 mA for each channel selected by the crosspoint
switch. For example, if four channels were to be summed on
one CWD output, the output would sink 9.6 mA dc and have a
full-scale current output of ±8 mA. The maximum number of
channels combined must be considered when setting the load
impedance for I/V conversion to ensure that the full-scale swing
and common-mode voltage are within the operating limits of
the AD9271. When interfacing to the AD8339, a common-
mode voltage of 2.5 V and a full-scale swing of 2.8 V p-p are
desired. This can be accomplished by connecting an inductor
between each CWD output and a 2.5 V supply, and then
connecting either a single-ended or differential load resistance
to the CWD± outputs. The value of resistance should be
calculated based on the maximum number of channels that can
be combined.
CWD± outputs are required under full-scale swing to be greater
than 1.5 V and less than CWVDD (3.3 V supply).
TGC OPERATION
The TGC signal path is fully differential throughout to maximize
signal swing and reduce even-order distortion; however, the LNAs
are designed to be driven from a single-ended signal source. Gain
values are referenced from the single-ended LNA input to the
differential ADC input. A simple exercise in understanding the
maximum and minimum gain requirements is shown in Figure 48.
LNA FS
(0.333V p-p SE)
ADC FS (2V p-p)
~5dB MARGIN
>8dB MARGIN
ADC NOISE FLOOR
(224V rms)
MINIMUM GAIN
MAXIMUM GAIN
063
04-
09
7
LNA
ADC
70dB
87dB
VGA GAIN RANGE > 30dB
MAX CHANNEL GAIN > 40dB
Figure 48. Gain Requirements of TGC for a 12-Bit, 40 MSPS ADC
In summary, the maximum gain required is determined by
(ADC Noise Floor/VGA Input Noise Floor) + Margin =
20 log(224/5.4) + 8 dB = 40.3 dB
The minimum gain required is determined by
(ADC Input FS/VGA Input FS) + Margin =
20 log(2/0.333) – 5 dB = 10.6 dB
Therefore, a 12-bit, 40 MSPS ADC with 15 MHz of bandwidth
should suffice in achieving the dynamic range required for most
of today’s ultrasound systems.
The system gain is distributed as listed in Table 8.
Table 8. Channel Gain Distribution
Section
Nominal Gain (dB)
LNA
14/15.6/18
Attenuator
0 to 30
VGA Amp
24
Filter
0
ADC
0
Total
8.4 to 38.4/10 to 40/12.4 to 42.4
The linear-in-dB gain (law conformance) range of the TGC path
is 30 dB, extending from 10 dB to 40 dB. The slope of the gain
control interface is 31.6 dB/V, and the gain control range is 0 V
to 1 V as specified in Equation 3. Equation 4 is the expression
for channel gain.
5
.
0
)
(
)
(
)
(
+
+
=
GAIN
V
GAIN
(3)
ICPT
V
dB
Gain
GAIN +
=
V
dB
6
.
31
)
(
(4)
where ICPT is the intercept point of the TGC gain.
In its default condition, the LNA has a gain of 15.6 dB (6×) and
the VGA gain is 6 dB if the voltage on the GAIN± pins is 0 V.
This gives rise to a total gain (or ICPT) of 10 dB through the
TGC path if the LNA input is unmatched, or of 4 dB if the LNA
is matched to 50 Ω (RFB = 200 Ω). If the voltage on the GAIN±
pins is 1 V, however, the VGA gain is 24 dB. This gives rise to a
total gain of 40 dB through the TGC path if the LNA input is
unmatched, or of 34 dB if the LNA input is matched.
Each LNA output is dc-coupled to a VGA input. The VGA consists
of an attenuator with a range of 30 dB followed by an amplifier
with 24 dB of gain for a net gain range of 6 dB to +24 dB. The
X-AMP gain-interpolation technique results in low gain error
and uniform bandwidth, and differential signal paths minimize
distortion.
At low gains, the VGA should limit the system noise perfor-
mance (SNR); at high gains, the noise is defined by the source and
LNA. The maximum voltage swing is bound by the full-scale
peak-to-peak ADC input voltage (2 V p-p).
Both the LNA and VGA have limitations within each section of
the TGC path, depending on the voltage applied to the GAIN+ and
GAIN pins. The LNA has three limitations, or full-scale settings,
depending on the gain selection applied through the SPI interface.
When a voltage of 0.2 V or less is applied to the GAIN± pins, the
LNA operates near the full-scale input range to maximize the
dynamic range of the ADC without clipping the signal. When
more than 0.2 V is applied to the GAIN± pins, the input signal to
the LNA must be lowered to keep it within the full-scale range
of the ADC (see Figure 49).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-J61-MW-B1 | CONVERTER MOD DC/DC 12V 100W |
| LTC1323CS16#PBF | IC TXRX EIA562 5V SINGLE 16-SOIC |
| MS3100E22-11P | CONN RCPT 2POS WALL MNT W/PINS |
| VI-BNH-MW-F4 | CONVERTER MOD DC/DC 52V 100W |
| LTC1323CS16 | IC TXRX EIA562 5V SINGLE 16-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9271BSVZRL-40 | 功能描述:IC ADC OCT 12BIT 40MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD9271BSVZRL-50 | 功能描述:IC ADC OCT 12BIT 50MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD9271BSVZRL7-25 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9271BSVZRL7-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
| AD9271BSVZRL7-50 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。