參數(shù)資料
型號(hào)： AD9262BCPZRL7-10
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 10MHZ 64LFCSP
設(shè)計(jì)資源： Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062)
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 16
采樣率（每秒）： 160M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 762mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，雙極；1 個(gè)差分，單極
AD9262
Rev. A | Page 18 of 32
External Reference Operation
If an external reference is desired, the internal reference can be
disabled by setting Serial Register 0x18[6] high. Figure 49 shows
an application using the ADR130B as a stable external reference.
0.5V
ADR130B
TO CURRENT
GENERATOR
0.1F
10F
AVDD
10k
07
77
2-
0
45
Figure 49. External Reference Configuration
CLOCK INPUT CONSIDERATIONS
The AD9262 offers two modes of sourcing the ADC sample
clock (CLK+ and CLK). The first mode uses an on-chip clock
multiplier that accepts a reference clock operating at the lower
input frequency. The on-chip phase-locked loop (PLL) then
multiplies the reference clock to a higher frequency, which is
then used to generate all the internal clocks required by the ADC
The clock multiplier provides a high quality clock that meets
the performance requirements of most applications. Using the
on-chip clock multiplier removes the burden of generating and
distributing the high speed clock.
The second mode bypasses the clock multiplier circuitry and
allows the clock to be directly sourced. This mode enables the
user to source a very high quality clock directly to the Σ-Δ
modulator. Sourcing the ADC clock directly may be necessary
in demanding applications that require the lowest possible ADC
output noise. See Figure 28, which shows the degradation in
SNR performance for the various PLL settings.
In either case, when using the on-chip clock multiplier or sourcing
the high speed clock directly, it is necessary that the clock
source have low jitter to maximize the ADC noise performance.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. As jitter increases, the SNR performance of the
AD9262 degrades from that specified in Table 2. The jitter
inherent in the part due to the PLL root sum squares with any
external clock jitter, thereby degrading performance. To prevent
jitter from dominating the performance of the AD9262, the input
clock source should be no greater than 1 ps rms of jitter.
The CLK± inputs are self-biased to 450 mV (see Figure 31);
if the inputs are dc-coupled, it is important to maintain the
specified 450 mV input common-mode voltage. Each input pin
can safely swing from 200 mV p-p to 1 V p-p single-ended
about the 450 mV common-mode voltage. The recommended
clock inputs are CMOS or LVPECL.
The specified clock rate of the Σ-Δ modulator, fMOD, is 640 MHz.
The clock rate possesses a direct relationship to the available
input bandwidth of the ADC.
Bandwidth = fMOD ÷ 64
In either case, using the on-chip clock multiplier to generate the
Σ-Δ modulator clock rate or directly sourcing the clock, any
deviation from 640 MHz results in a change in input band-
width. The input range of the clock is limited to 640 MHz ± 5%.
In situations where the AD9262 loses its clock and then later
regains it, it is important that the sample rate converter be reset
and reprogrammed before the desired output data rate is
achieved.
Direct Clocking
The default configuration of the AD9262 is for direct clocking
where the PLL is bypassed. Figure 50 shows one preferred method
for clocking the AD9262. A low jitter clock source is converted
from a single-ended signal to a differential signal using an RF
transformer. The back-to-back Schottky diodes across the
secondary side of the transformer limits clock excursions into the
AD9262 to approximately 0.8 V p-p differential. This helps
prevent the large voltage swings of the clock from feeding
through to other portions of the AD9262 while preserving the
fast rise and fall times of the signal, which are critical to
achieving low jitter.
CLOCK
INPUT
XFMR
MINI-CIRCUITS
TC1-1-13M+, 1:1
SCHOTTKY
DIODES:
HSM2812
50
CLK+
CLK–
0.1F
ADC
AD9262
0.1F
0
77
72
-0
46
Figure 50. Transformer-Coupled Differential Clock
If a differential clock is not available, the AD9262 can be driven
by a single-ended signal into the CLK+ terminal with the CLK
terminal ac-coupled to ground. Figure 51 shows the circuit
configuration.
SCHOTTKY
DIODES:
HSM2812
50
CLK+
CLK–
0.1F
ADC
AD9262
CLOCK
INPUT
0
77
72
-0
47
Figure 51. Single-Ended Clock
Another option is to ac couple a differential LVPECL signal to
the sample clock input pins, as shown in Figure 52. The AD951x
family of clock drivers is recommended because it offers excellent
jitter performance.
100
240
501
150 RESISTORS ARE OPTIONAL.
501
CLK+
CLK–
0.1F
ADC
AD9262
CLOCK
INPUT
CLOCK
INPUT
0.1F
CLK
AD951x
LVPECL
DRIVER
CLK
0
7772
-0
48
Figure 52. Differential LVPECL Sample Clock
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AD9262BCPZRL7-5 功能描述:IC ADC 16BIT 5MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
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