參數資料
型號: AD9252-50EBZ
廠商: Analog Devices Inc
文件頁數: 45/52頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9252
設計資源: AD9212/22/52 Gerber Files
標準包裝: 1
ADC 的數量: 8
位數: 14
采樣率(每秒): 50M
數據接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標準): 748mW @ 50MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9252-50
已供物品:
Data Sheet
AD9252
Rev. E | Page 5 of 52
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Table 3.
AD9252-50
Parameter1
Temperature
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
250
mV p-p
Input Common-Mode Voltage
Full
1.2
V
Input Resistance (Differential)
25°C
20
k
Input Capacitance
25°C
1.5
pF
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Full
1.2
3.6
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
30
k
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
3.6
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
70
k
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Full
1.2
DRVDD + 0.3
V
Logic 0 Voltage
Full
0
0.3
V
Input Resistance
25°C
30
k
Input Capacitance
25°C
2
pF
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Full
1.79
V
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
DIGITAL OUTPUTS (D + x, D x), (ANSI-644)
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
454
mV
Output Offset Voltage (VOS)
Full
1.125
1.375
V
Output Coding (Default)
Offset binary
DIGITAL OUTPUTS (D + x, D x),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
250
mV
Output Offset Voltage (VOS)
Full
1.10
1.30
V
Output Coding (Default)
Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.
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